Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 167
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 8-6: PBxDIV: PERIPHERAL BUS ‘x’ CLOCK DIVISOR CONTROL REGISTER (‘x’ = 1-7)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-1 U-0 U-0 U-0 R-1 U-0 U-0 U-0
ON
(1)
— — — PBDIVRDY — — —
7:0
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— PBDIV<6:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Peripheral Bus ‘x’ Output Clock Enable bit
(1)
1 = Output clock is enabled
0 = Output clock is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11 PBDIVRDY: Peripheral Bus ‘x’ Clock Divisor Ready bit
1 = Clock divisor logic is not switching divisors and the PBxDIV<6:0> bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV<6:0> bits cannot be written
bit 10-7 Unimplemented: Read as ‘0’
bit 6-0 PBDIV<6:0>: Peripheral Bus ‘x’ Clock Divisor Control bits
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x
 7)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x = 7)
Note 1: The clock for peripheral bus 1 cannot be turned off. Therefore, the ON bit in the PB1DIV register cannot
be written as a ‘0’.
Note: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.