Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 164 Preliminary  2015 Microchip Technology Inc.
bit 10-8 PLLIDIV<2:0>: System PLL Input Clock Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
The default setting is specified by the FPLLIDIV<2:0> Configuration bits in the DEVCFG2 register. If the
PLLICLK is set for FRC, this setting is ignored by the PLL and the divider is set for Divide-by-1. Refer to
Register 34-5 in Section 34.0 “Special Features” for information.
bit 7 PLLICLK: System PLL Input Clock Source bit
1 = FRC is selected as the input to the System PLL
0 = P
OSC is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information.
bit 6-3 Unimplemented: Read as ‘0’
bit 2-0 PLLRANGE<2:0>: System PLL Frequency Range Selection bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
The default setting is specified by the FPLLRNG<2:0> Configuration bits in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information.
REGISTER 8-3: SPLLCON: SYSTEM PLL CONTROL REGISTER
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0> = 001).