Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 163
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 8-3: SPLLCON: SYSTEM PLL CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-y R/W-y R/W-y
— — — — — PLLODIV<2:0>
23:16
U-0 R/W-y R/W-y R/W-y R/W-y R/W-y R/W-y R/W-y
— PLLMULT<6:0>
15:8
U-0 U-0 U-0 U-0 U-0 R/W-y R/W-y R/W-y
— PLLIDIV<2:0>
7:0
R/W-y U-0 U-0 U-0 U-0 R/W-y R/W-y R/W-y
PLLICLK — — — — PLLRANGE<2:0>
Legend: y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits
111 = PLL Divide by 32
110 = PLL Divide by 32
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = PLL Divide by 2
The default setting is specified by the FPLLODIV<2:0> Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 “Special Features” for information.
bit 23 Unimplemented: Read as ‘0’
bit 22-16 PLLMULT<6:0>: System PLL Multiplier bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
The default setting is specified by the FPLLMULT<6:0> Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 “Special Features” for information.
bit 15-11 Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0> = 001).