Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 161

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family

bit 10-8 NOSC<2:0>: New Oscillator Selection bits

111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

110 = Reserved

101 = Internal Low-Power RC (LPRC) Oscillator

100 = Secondary Oscillator (S

OSC)

011 = Reserved

010 = Primary Oscillator (POSC) (HS or EC)

001 = System PLL (SPLL)

000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (DEVCFG1<2:0>).

bit 7 CLKLOCK: Clock Selection Lock Enable bit

1 = Clock and PLL selections are locked

0 = Clock and PLL selections are not locked and may be modified

bit 6-5 Unimplemented: Read as ‘0’

bit 4 SLPEN: Sleep Mode Enable bit

1 = Device will enter Sleep mode when a WAIT instruction is executed

0 = Device will enter Idle mode when a WAIT instruction is executed

bit 3 CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

bit 2 Unimplemented: Read as ‘0’

bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit

1 = Enable Secondary Oscillator

0 = Disable Secondary Oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

(1)

1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1: The reset value for this bit depends on the setting of the IESO (DEVCFG1<7>) bit. When IESO = 1, the

reset value is ‘1’. When IESO = 0, the reset value is ‘0’.

Note: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced

PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.