Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 156 Preliminary  2015 Microchip Technology Inc.
FIGURE 8-1: PIC32MZ EF FAMILY OSCILLATOR DIAGRAM
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals, or to eliminate clipping. Alternately, to increase oscillator circuit gain,
add a parallel resistor, R
P.
2. The internal feedback resistor, R
F, is typically in the range of 2 to 10 M
3. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for help in
determining the best oscillator components.
4. PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
5. Shaded regions indicate multiple instantiations of a peripheral or feature.
6. Refer to Table 37-19 in Section 37.0 “Electrical Characteristics” for frequency limitations.
Timer1, RTCC
Clock Control Logic
Fail-Safe
Clock
Monitor
FSCM INT
FSCM Event
COSC<2:0>
NOSC<2:0>
OSWEN
FCKSM<1:0>
Secondary Oscillator (SOSC)
SOSCEN
SOSCO
SOSCI
POSC (HS, EC)
FRCDIV<2:0>
WDT, RTCC
8 MHz typical
32.768 kHz
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
FRCDIV
TUN<5:0>
Postscaler
PLLIDIV<2:0>
PLLICLK
FIN
(6)
PLLODIV<2:0>
32.768 kHz
PLLMULT<6:0>
SYSCLK

N

Backup FRC
Oscillator
8 MHz typical
BFRC
N

(N)
(N)
(N)
REFCLKOx
OE
To SPI,
Reference Clock
(5)
RODIV<14:0> (N)
ROTRIM<8:0> (M)
N
SPLL
REFCLKIx
POSC
FRC
LPRC
S
OSC
PBCLK1
SYSCLK
ROSEL<3:0>
Peripheral Bus Clock
(5)
Peripherals,
PBxDIV<6:0>
Postscaler
PBCLKx
(N)
C1
(3)
C2
(3)
XTAL
R S
(1)
Enable
OSC2
(4)
OSC1
R
F
(2)
Primary Oscillator (POSC)
R
P
(1)
(M)
PLL x M
USB Clock (USBCLK)
USB PLL
UPLLFSEL
FPLL
(6)
BFRC
PLLRANGE<2:0>
To ADC and Flash
ADC,
SQI
FVco
(6)
System PLL
From P
OSC
(12 or 24 MHz only)
CPU
‘x’ = 1-5, 7, 8
F
REF
(6)
‘x’ = 1-4
REFOxCON
REFOxTRIM
2N
M
512
----------+




SPLL
Fsys
(6)
Clock
Switch/
Slew
POSCBOOST
POSCGAIN<1:0>
SOSCBOOST
SOSCGAIN<1:0>