Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 116 Preliminary 2015 Microchip Technology Inc.
7.1 CPU Exceptions
CPU coprocessor 0 contains the logic for identifying and managing exceptions.
Exceptions can be caused by a variety of sources, including boundary cases in
data, external events or program errors.
Table 7-1 lists the exception types in
order of priority.
TABLE 7-1: MIPS32
®
M-CLASS MICROPROCESSOR CORE EXCEPTION TYPES
Exception Type
(In Order of
Priority)
Description Branches to
Status
Bits Set
Debug Bits
Set
EXCCODE XC32 Function Name
Highest Priority
Reset Assertion MCLR or a Power-on Reset (POR). 0xBFC0_0000 BEV, ERL — — _on_reset
Soft Reset Assertion of a software Reset. 0xBFC0_0000 BEV, SR,
ERL
— — _on_reset
DSS EJTAG debug single step. 0xBFC0_0480 — DSS — —
DINT EJTAG debug interrupt. Caused by the assertion of
the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
0xBFC0_0480 — DINT — —
NMI Assertion of NMI signal. 0xBFC0_0000 BEV, NMI,
ERL
— — _nmi_handler
Machine Check TLB write that conflicts with an existing entry. EBASE+0x180 MCHECK,
EXL
— 0x18 _general_exception_handler
Interrupt Assertion of unmasked hardware or software inter-
rupt signal.
See Table 7-2. IPL<2:0> — 0x00 See Tab le 7-2.
Deferred Watch Deferred watch (unmasked by K|DM=>!(K|DM)
transition).
EBASE+0x180 WP, EXL — 0x17 _general_exception_handler
DIB EJTAG debug hardware instruction break matched. 0xBFC0_0480 — DIB — —
WATCH A reference to an address that is in one of the
Watch registers (fetch).
EBASE+0x180 EXL — 0x17 _general_exception_handler
AdEL Fetch address alignment error. Fetch reference to
protected address.
EBASE+0x180 EXL — 0x04 _general_exception_handler
TLBL Fetch TLB miss or fetch TLB hit to page with V = 0. EBASE if Status.EXL = 0 — — 0x02 —
EBASE+0x180 if
Status.EXL == 1
— — 0x02 _general_exception_handler
TLBL Execute
Inhibit
An instruction fetch matched a valid TLB entry that
had the XI bit set.
EBASE+0x180 EXL — 0x14 _general_exception_handler
Cache Error Instruction or data reference detects a cache tag or
data error.
EBASE+0x100 — — 0x1E _cache_error_exception