Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 115
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
7.0 CPU EXCEPTIONS AND
INTERRUPT CONTROLLER
PIC32MZ EF devices generate interrupt requests in
response to interrupt events from peripheral modules.
The Interrupt Controller module exists outside of the
CPU and prioritizes the interrupt events before
presenting them to the CPU.
The CPU handles interrupt events as part of the excep-
tion handling mechanism, which is described in
Section 7.1 “CPU Exceptions”.
The Interrupt Controller module includes the following
features:
• Up to 213 interrupt sources and vectors with
dedicated programmable offsets, eliminating the
need for redirection
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
vector
• Four user-selectable subpriority levels within each
priority
• Seven shadow register sets that can be used for any
priority level, eliminating software context switch and
reducing interrupt latency
• Software can generate any interrupt
Figure 7-1 shows the block diagram for the Interrupt
Controller and CPU exceptions.
FIGURE 7-1: CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MZ EF family of devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 8. “Interrupt Controller”
(DS60001108) and Section 50. “CPU
for Devices with MIPS32
®
microAptiv™ and M-Class Cores”
(DS60001192) of the “PIC32 Family
Reference Manual”, which
is available
from the Microchip web site
(www.microchip.com/PIC32).
Interrupt Controller
Interrupt Requests
Vector Number and Offset
CPU Core
Priority Level
Shadow Set Number
SYSCLK
(Exception Handling)