Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 113
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 6-3: RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — —DMTOWDTO
23:16
R/W-0 U-0 U-0 U-0
R/W-0
U-0
R/W-0 R/W-0
SWNMI — — —GNMI —CFWDTS
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NMICNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NMICNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25 DMTO: Deadman Timer Time-out Flag bit
1 = DMT time-out has occurred and caused a NMI
0 = DMT time-out has not occurred
Setting this bit will cause a DMT NMI event, and NMICNT will begin counting.
bit 24 WDTO: Watchdog Timer Time-Out Flag bit
1 = WDT time-out has occurred and caused a NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event, and MNICNT will begin counting.
bit 23 SWNMI: Software NMI Trigger.
1 = An NMI will be generated
0 = An NMI will not be generated
bit 22-20 Unimplemented: Read as ‘0’
bit 19 GNMI: General NMI bit
1 = A general NMI event has been detected or a user-initiated NMI event has occurred
0 = A general NMI event has not been detected
Setting GNMI to a ‘1’ causes a user-initiated NMI event. This bit is also set by writing 0x4E to the
NMIKEY<7:0> (INTCON<31:24>) bits.
bit 18 Unimplemented: Read as ‘0’
bit 17 CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
Setting this bit will cause a a CF NMI event, but will not cause a clock switch to the BFRC.
bit 16 WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit
1 = WDT time-out has occurred during Sleep mode and caused a wake-up from sleep
0 = WDT time-out has not occurred during Sleep mode
Setting this bit will cause a WDT NMI.
bit 15-0 NMICNT<15:0>: NMI Reset Counter Value bits
1111111111111111-0000000000000001 = Number of SYSCLK cycles before a device Reset occurs
(1)
0000000000000000 = No delay between NMI assertion and device Reset event
Note 1: When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered
the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset. This NMI reset
counter is only applicable to these two specific NMI events.
Note: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
42. “Oscillators with Enhanced PLL” in the “PIC32 Family Reference Manual” for details.