Datasheet

2015 Microchip Technology Inc. Preliminary DS60001320B-page 107
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 5-8: NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LBWPULOCK LBWP4
(1)
LBWP3
(1)
LBWP2
(1)
LBWP1
(1)
LBWP0
(1)
7:0
R/W-1 r-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
UBWPULOCK UBWP4
(1)
UBWP3
(1)
UBWP2
(1)
UBWP1
(1)
UBWP0
(1)
Legend: r = Reserved
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0
bit 15 LBWPULOCK: Lower Boot Alias Write-protect Unlock bit
1 = LBWPx bits are not locked and can be modified
0 = LBWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 14-13 Unimplemented: Read as ‘0
bit 12 LBWP4: Lower Boot Alias Page 4 Write-protect bit
(1)
1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled
bit 11 LBWP3: Lower Boot Alias Page 3 Write-protect bit
(1)
1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled
bit 10 LBWP2: Lower Boot Alias Page 2 Write-protect bit
(1)
1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled
bit 9 LBWP1: Lower Boot Alias Page 1 Write-protect bit
(1)
1 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF enabled
0 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF disabled
bit 8 LBWP0: Lower Boot Alias Page 0 Write-protect bit
(1)
1 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF enabled
0 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF disabled
bit 7 UBWPULOCK: Upper Boot Alias Write-protect Unlock bit
1 = UBWPx bits are not locked and can be modified
0 = UBWPx bits are locked and cannot be modified
This bit is only user-clearable and cannot be set except by any reset.
bit 6 Reserved: This bit is reserved for use by development tools
bit 5 Unimplemented: Read as ‘0
Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.
Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.