Datasheet
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 104 Preliminary 2015 Microchip Technology Inc.
REGISTER 5-3: NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<31:24>
23:16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<23:16>
15:8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<15:8>
7:0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMKEY<31:0>: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read
Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
REGISTER 5-4: NVMADDR: FLASH ADDRESS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<31:24>
(1)
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<23:16>
(1)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<15:8>
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<7:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMADDR<31:0>: Flash Address bits
(1)
Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.
NVMOP<3:0>
Selection
Flash Address Bits (NVMADDR<31:0>)
Page Erase Address identifies the page to erase (NVMADDR<13:0> are ignored).
Row Program Address identifies the row to program (NVMADDR<10:0> are ignored).
Word Program Address identifies the word to program (NVMADDR<1:0> are ignored).
Quad Word Program Address identifies the quad word (128-bit) to program (NVMADDR<3:0> bits are
ignored).
Note 1: For all other NVMOP<3:0> bit settings, the Flash address is ignored. See the NVMCON
register (Register 5-1) for additional information on these bits.