Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 101
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 5-1: NVMCON: FLASH PROGRAMMING CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0, HC R/W-0 R-0, HS, HC R-0, HS, HC U-0 U-0 U-0 U-0
WR
(1)
WREN
(1)
WRERR
(1)
LVDERR
(1)
— — — —
7:0
R/W-0 R/W-x U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
PFSWAP BFSWAP — —NVMOP<3:0>
Legend: HC = Hardware Set HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 WR: Write Control bit
(1)
This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been
performed.
1 = Initiate a Flash operation
0 = Flash operation is complete or inactive
bit 14 WREN: Write Enable bit
(1)
1 = Enable writes to the WR bit and disables writes to the NVMOP<3:0> bits
0 = Disable writes to WR bit and enables writes to the NVMOP<3:0> bits
bit 13 WRERR: Write Error bit
(1)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit
(1)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11-8 Unimplemented: Read as ‘0’
bit 7 PFSWAP: Program Flash Bank Swap Control bit
This bit is only writable when WREN = 0 and the unlock sequence has been performed.
1 = Program Flash Bank 2 is mapped to the lower mapped region and program Flash Bank 1 is mapped to
the upper mapped region
0 = Program Flash Bank 1 is mapped to the lower mapped region and program Flash Bank 2 is mapped to
the upper mapped region
Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
2: This operation results in a “no operation” (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON<1:0> (DVCFG0<9:8>)), which enables ECC at all times. For all other FECCCON<1:0> bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON<1:0> = 01). Refer to Section 52. “Flash Program Memory
with Support for Live Update” (DS60001193) for information regarding ECC and Flash programming.