PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU, Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog Operating Conditions Advanced Analog Features • 2.1V to 3.6V, -40ºC to +85ºC, DC to 200 MHz • 2.1V to 3.
PIC32MZ EF FAMILY FEATURES Y 8/18 PIC32MZ0512EFE100 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 128 Preliminary PIC32MZ0512EFK100 100 PIC32MZ1024EFE100 PIC32MZ1024EFF100 160 51 9/9/9 6 6 5 2 N Y PIC32MZ1024EFK100 2 Y Y 8/18 PIC32MZ0512EFE124 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 PIC32MZ0512EFF124 1024 TQFP 512 256 128 PIC32MZ0512EFK124 124 PIC32MZ1024EFE124 PIC32MZ1024EFF124 160 53 9/9/9 6 6 5 2 N Y PIC32MZ1024EFK124
PIC32MZ EF FAMILY FEATURES (CONTINUED) 8/16 2 N Y 2 Y Y 8/18 PIC32MZ1024EFG100 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 1024 PIC32MZ1024EFM100 Preliminary 512 PIC32MZ2048EFG100 PIC32MZ2048EFH100 100 TQFP 160 51 9/9/9 6 6 5 2 N Y PIC32MZ2048EFM100 2 Y Y 8/18 PIC32MZ1024EFG124 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 PIC32MZ1024EFH124 2048 1024 PIC32MZ1024EFM124 512 PIC32MZ2048EFG124 PIC32MZ2048EFH124 124 VTLA 160 53 9/9
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Device Pin Tables TABLE 2: PIN NAMES FOR 64-PIN DEVICES 64-PIN QFN(4) AND TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)064 PIC32MZ1024EF(G/H/M)064 PIC32MZ1024EF(E/F/K)064 PIC32MZ2048EF(G/H/M)064 64 64 1 QFN(4) Pin # Full Pin Name 1 TQFP Pin # Full Pin Name 1 AN17/ETXEN/RPE5/PMD5/RE5 33 VBUS 2 AN16/ETXD0/PMD6/RE6 34 VUSB3V3 3 AN15/ETXD1/PMD7/RE7 35 VSS 4 AN14/C1IND/RPG6/SCK2/PMA5/RG6 36 D- 5 AN13/C1INC/RPG7/SDA4/PMA4/RG7
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 3: PIN NAMES FOR 100-PIN DEVICES 100-PIN TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)100 PIC32MZ1024EF(G/H/M)100 PIC32MZ1024EF(E/F/K)100 PIC32MZ2048EF(G/H/M)100 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 AN23/AERXERR/RG15 36 VSS 2 EBIA5/AN34/PMA5/RA5 37 VDD 3 EBID5/AN17/RPE5/PMD5/RE5 38 TCK/EBIA19/AN29/RA1 4 EBID6/AN16/PMD6/RE6 39 TDI/EBIA18/AN30/RPF13/SCK5/RF13 5 EBID7/AN15/PMD7/RE7 40 TDO/EBIA17/AN31/RPF12/RF12
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 3: PIN NAMES FOR 100-PIN DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)100 PIC32MZ1024EF(G/H/M)100 PIC32MZ1024EF(E/F/K)100 PIC32MZ2048EF(G/H/M)100 100 1 Pin # Full Pin Name Pin # Full Pin Name 71 EMDIO/AEMDIO/RPD0/RTCC/INT0/RD0 86 EBID10/ETXD0/RPF1/PMD10/RF1 72 SOSCI/RPC13/RC13 87 EBID9/ETXERR/RPG1/PMD9/RG1 73 SOSCO/RPC14/T1CK/RC14 88 EBID8/RPG0/PMD8/RG0 74 VDD 89 TRCLK/SQICLK/RA6 75 VSS 90 T
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 4: PIN NAMES FOR 124-PIN DEVICES A34 124-PIN VTLA (BOTTOM VIEW) A17 B29 B13 PIC32MZ0512EF(E/F/K)124 PIC32MZ1024EF(G/H/M)124 PIC32MZ1024EF(E/F/K)124 PIC32MZ2048EF(G/H/M)124 B56 Full Pin Name A51 A1 A68 Polarity Indicator Package Pin # B41 B1 Package Pin # Full Pin Name A1 No Connect A35 A2 AN23/RG15 A36 VBUS VUSB3V3 A3 EBID5/AN17/RPE5/PMD5/RE5 A37 D- A4 EBID7/AN15/PMD7/RE7 A38 RPF3/USBID/RF3 A5 AN35/ETXD0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 4: PIN NAMES FOR 124-PIN DEVICES (CONTINUED) A34 124-PIN VTLA (BOTTOM VIEW) A17 B13 PIC32MZ0512EF(E/F/K)124 PIC32MZ1024EF(G/H/M)124 PIC32MZ1024EF(E/F/K)124 PIC32MZ2048EF(G/H/M)124 Full Pin Name B41 B1 B56 A51 A1 A68 Polarity Indicator Package Pin # B29 Package Pin # Full Pin Name B1 EBIA5/AN34/PMA5/RA5 B29 VSS B2 EBID6/AN16/PMD6/RE6 B30 D+ B3 EBIA6/AN22/RPC1/PMA6/RC1 B31 RPF2/SDA3/RF2 B4 AN36/ETXD1/RJ9 B32
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 5: PIN NAMES FOR 144-PIN DEVICES 144-PIN LQFP AND TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)144 PIC32MZ1024EF(G/H/M)144 PIC32MZ1024EF(E/F/K)144 PIC32MZ2048EF(G/H/M)144 144 1 Pin Number Full Pin Name Pin Number Full Pin Name 1 AN23/RG15 37 PGEC2/AN46/RPB6/RB6 2 EBIA5/AN34/PMA5/RA5 38 PGED2/AN47/RPB7/RB7 3 EBID5/AN17/RPE5/PMD5/RE5 39 VREF-/CVREF-/AN27/RA9 4 EBID6/AN16/PMD6/RE6 40 VREF+/CVREF+/AN28/RA10 5 6 EBID7/AN15/P
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 5: PIN NAMES FOR 144-PIN DEVICES (CONTINUED) 144-PIN LQFP AND TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)144 PIC32MZ1024EF(G/H/M)144 PIC32MZ1024EF(E/F/K)144 PIC32MZ2048EF(G/H/M)144 144 1 Pin Number Full Pin Name Pin Number Full Pin Name 73 VBUS 109 RPD1/SCK1/RD1 74 VUSB3V3 75 VSS 110 111 EBID14/RPD2/PMD14/RD2 EBID15/RPD3/PMD15/RD3 76 D- 77 D+ 112 113 EBID12/RPD12/PMD12/RD12 EBID13/PMD13/RD13 78 RPF3/USBID/RF3 79 SDA
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 37 3.0 CPU........................................................
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Referenced Sources This device data sheet is based on the following individual sections of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • To access the documents listed below, browse the documentation section of the Microchip website (www.microchip.com).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 14 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 1.0 DEVICE OVERVIEW Note: This data sheet contains device-specific information for PIC32MZ EF devices. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-1: ADC PINOUT I/O DESCRIPTIONS Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA Pin Type 144-pin TQFP/ LQFP Buffer Type AN0 16 25 A18 36 I Analog AN1 15 24 A17 35 I Analog AN2 14 23 A16 34 I Analog AN3 13 22 A14 31 I Analog AN4 12 21 A13 26 I Analog AN5 23 34 B19 49 I Analog AN6 24 35 A24 50 I Analog AN7 27 41 A27 59 I Analog AN8 28 42 B23 60 I Anal
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-1: ADC PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP AN36 — — B4 8 I Analog AN37 — — B12 27 I Analog AN38 — — B17 43 I Analog AN39 — — A22 44 I Analog AN40 — — A30 65 I Analog AN41 — — B26 66 I Analog Pin Name 124-pin VTLA 144-pin TQFP/ LQFP AN42 — — A31 67 I Analog AN45 11 20 B11 25 I Analog AN46 17 26 B14 37 I A
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-2: OSCILLATOR PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type CLKI 31 49 B28 71 I CLKO 32 50 A33 72 O OSC1 31 49 B28 71 I OSC2 32 50 A33 72 O SOSCI 47 72 B41 105 I Pin Name SOSCO 48 73 A49 106 REFCLKI1 PPS PPS PPS PPS REFCLKI3 PPS PPS PPS PPS REFCLKI4 PPS PPS PPS PPS REFCLKO1 PPS PPS PPS PPS REFCLKO3 PPS PPS PPS PPS REFCLKO4 PPS PPS PPS PP
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-4: OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP OC1 PPS PPS PPS PPS O — OC2 PPS PPS PPS PPS O — OC3 PPS PPS PPS PPS O — OC4 PPS PPS PPS PPS O — OC5 PPS PPS PPS PPS O — OC6 PPS PPS PPS PPS O — OC7 PPS PPS PPS PPS O — OC8 PPS PPS PPS PPS O — OC9 PPS PPS PPS PPS O — OCFA PPS PP
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type RA0 — 17 A11 22 I/O ST RA1 — 38 B21 56 I/O ST RA2 — 59 A41 85 I/O ST RA3 — 60 B34 86 I/O ST RA4 — 61 A42 87 I/O ST RA5 — 2 B1 2 I/O ST RA6 — 89 A61 129 I/O ST RA7 — 90 B51 130 I/O ST RA9 — 28 B15 39 I/O ST RA10 — 29 A20 40 I/O ST R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type RD0 46 71 A48 104 I/O ST RD1 49 76 A52 109 I/O ST Pin Name Buffer Type Description PORTD RD2 50 77 B42 110 I/O ST RD3 51 78 A53 111 I/O ST RD4 52 81 A56 118 I/O ST RD5 53 82 B46 119 I/O ST RD6 — — A57 120 I/O ST RD7 — — B47 121 I/O
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type RG0 — 88 B50 128 I/O ST RG1 — 87 A60 127 I/O ST RG6 4 10 B6 14 I/O ST RG7 5 11 A8 15 I/O ST RG8 6 12 B7 16 I/O ST RG9 10 16 B9 21 I/O ST RG12 — 96 A65 140 I/O ST RG13 — 97 B55 141 I/O ST RG14 — 95 B54 139 I/O ST RG15 — 1 A2
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type RK0 — — — 19 I/O ST RK1 — — — 51 I/O ST RK2 — — — 52 I/O ST RK3 — — — 53 I/O ST RK4 — — — 92 I/O ST RK5 — — — 93 I/O ST RK6 — — — 94 I/O ST RK7 — — — 126 I/O Pin Name Buffer Type Description PORTK Legend: CMOS = CMOS-compatible in
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-7: TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP T1CK 48 73 A49 106 I ST Timer1 External Clock Input T2CK PPS PPS PPS PPS I ST Timer2 External Clock Input T3CK PPS PPS PPS PPS I ST Timer3 External Clock Input T4CK PPS PPS PPS PPS I ST Timer4 External Clock Input T5CK PPS PPS PPS PPS I ST
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-8: UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA U1RX PPS PPS PPS PPS I ST U1TX PPS PPS PPS PPS O — UART1 Transmit U1CTS PPS PPS PPS PPS I ST UART1 Clear to Send U1RTS PPS PPS PPS PPS O — UART1 Ready to Send Pin Name 144-pin TQFP/ LQFP Description Universal Asynchronous Receiver Transmitter 1 UART1 Receive Universal Asyn
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-9: SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP SCK1 49 76 A52 109 I/O ST SPI1 Synchronous Serial Clock Input/Output SDI1 PPS PPS PPS PPS I ST SPI1 Data In SDO1 PPS PPS PPS PPS O — SPI1 Data Out SS1 PPS PPS PPS PPS I/O ST SPI1 Slave Synchronization Or Frame Pulse I/O Pin Name Description Serial Periphe
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-10: I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP SCL1 44 66 B37 95 I/O ST I2C1 Synchronous Serial Clock Input/Output SDA1 43 67 A45 96 I/O ST I2C1 Synchronous Serial Data Input/Output Pin Name Description Inter-Integrated Circuit 1 Inter-Integrated Circuit 2 SCL2 — 59 A41 85 I/O ST I2C2 Synchronous Serial Clock
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-12: PMP PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type Buffer Type PMA0 30 44 B24 30 I/O TTL/ST Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes) PMA1 29 43 A28 51 I/O TTL/ST Parallel Master Port Address bit 1 Input (Buffered Slave modes) and Output (Master modes) PMA2 10 16 B9 21 O — PMA3 6 12 B7 52
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP EBIA0 — 44 B24 30 O — EBIA1 — 43 A28 51 O — EBIA2 — 16 B9 21 O — EBIA3 — 12 B7 52 O — EBIA4 — 11 A8 68 O — EBIA5 — 2 B1 2 O — EBIA6 — 6 B3 6 O — EBIA7 — 33 A23 48 O — EBIA8 — 65 A44 91 O — EBIA9 — 64 B36 90 O — EBIA10 — 32 B18 47 O — EBIA11 — 41 A27 29 O
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type Buffer Type Description EBIOE — 9 A7 13 O — External Bus Interface Output Enable EBIRDY1 — 60 B34 86 I ST External Bus Interface Ready Input EBIRDY2 — 58 A39 84 I ST EBIRDY3 — 57 B45 116 I ST EBIRP — — — 45 O — External Bus Interface Flash Reset Pin EBIW
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-14: USB PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type 73 I Analog 74 P — B30 77 I/O Analog USB D+ A37 76 I/O Analog USB D- A38 78 I ST 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP VBUS 33 51 A35 VUSB3V3 34 52 A36 D+ 37 55 D- 36 54 USBID 38 56 Pin Name Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-tra
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-16: ETHERNET MII I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type Buffer Type ERXD0 61 41 B32 81 I ST Ethernet Receive Data 0 ERXD1 58 42 B26 66 I ST Ethernet Receive Data 1 ERXD2 57 43 A31 67 I ST Ethernet Receive Data 2 ERXD3 56 44 A40 82 I ST Ethernet Receive Data 3 ERXERR 64 35 A30 65 I ST Ethernet Receive Error Input Pin Name Desc
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-18: ALTERNATE ETHERNET MII PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type Buffer Type AERXD0 — 18 — — I ST Alternate Ethernet Receive Data 0 AERXD1 — 19 — — I ST Alternate Ethernet Receive Data 1 AERXD2 — 28 — — I ST Alternate Ethernet Receive Data 2 AERXD3 — 29 — — I ST Alternate Ethernet Receive Data 3 AERXERR — 1 — — I ST Alt
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-20: SQI1 PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type Buffer Type SQICLK 57 89 A61 129 O — Serial Quad Interface Clock SQICS0 52 81 A56 118 O — Serial Quad Interface Chip Select 0 SQICS1 53 82 B46 119 O — Serial Quad Interface Chip Select 1 SQID0 58 97 B55 141 I/O ST Serial Quad Interface Data 0 SQID1 61 96 A65 140 I/O ST Seri
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-22: JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 144-pin TQFP/ LQFP Pin Type TCK 27 38 B21 56 I ST JTAG Test Clock Input Pin TDI 28 39 A26 57 I ST JTAG Test Data Input Pin TDO 24 40 B22 58 O — JTAG Test Data Output Pin TMS 23 17 A11 22 I ST JTAG Test Mode Select Pin TRCLK 57 89 A61 129 O — Trace Clock TRD0 58 97
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 36 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS 2.2 The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Note 1: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION VDD 0.1 µF Ceramic VSS VDD VDD VSS MCLR VDD VSS VDD C PIC32 VSS VSS VUSB3V3(1) VDD VSS VDD Connect(2) VDD 0.1 µF Ceramic VSS VSS AVSS AVDD VDD 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(2) Note 1: If the USB module is not used, this pin must be connected to VSS.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.4 ICSP Pins 2.6 Trace The PGECx and PGEDx pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.9 2.9.1.2 Designing for High-Speed Peripherals The PIC32MZ EF family devices have peripherals that operate at frequencies much higher than typical for an embedded environment.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.9.1.3 EMI Suppression Considerations The use of LDO regulators is preferred to reduce overall system noise and provide a cleaner power source. However, when utilizing switching Buck/Boost regulators as the local power source for PIC32MZ EF devices, as well as in electrically noisy environments, users should evaluate the use of T-Filters (i.e., L-C-L) on the power pins, as shown in Figure 2-5.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-6 and Figure 2-7.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A block diagram of the PIC32MZ EF family processor core is shown in Figure 3-1.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.1 Architecture Overview The MIPS32 M-Class Microprocessor core in PIC32MZ EF family devices contains several logic blocks working together in parallel, providing an efficient high-performance computing engine.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The MIPS architecture defines that the result of a multiply or divide operation be placed in one of four pairs of HI and LO registers. Using the Move-From-HI (MFHI) and Move-From-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 3-3: Register Number 12 13 14 15 16 17 18 19 20-22 23 24 25 26 27 28 29 30 31 COPROCESSOR 0 REGISTERS (CONTINUED) Register Name Function Status IntCtl SRSCtl SRSMap View_IPL Processor status and control. Interrupt control of vector spacing. Shadow register set control. Shadow register mapping control. Allows the Priority Level to be read/written without extracting or inserting that bit from/to the Status register.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.1.4 FLOATING POINT UNIT (FPU) TABLE 3-4: The Floating Point Unit (FPU), Coprocessor (CP1), implements the MIPS Instruction Set Architecture for floating point computation. The implementation supports the ANSI/IEEE Standard 754 (IEEE for Binary Floating Point Arithmetic) for single- and double-precision data formats. The FPU can be programmed to have thirty-two 32-bit or 64-bit floating point registers used for floating point operations.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The FPU implements a high-performance 7-stage pipeline: • Decode, register read and unpack (FR stage) • Multiply tree - double pumped for double (M1 stage) • Multiply complete (M2 stage) • Addition first step (A1 stage) • Addition second and final step (A2 stage) • Packing to IEEE format (FP stage) • Register writeback (FW stage) Table 3-5 lists the Coprocessor 1 Registers for the FPU.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.4 EJTAG Debug Support 3.6 The processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.7 M-Class Core Configuration Register 3-1 through Register 3-4 show the default configuration of the M-Class core, which is included on PIC32MZ EF family devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-2: Bit Range 31:24 23:16 15:8 7:0 CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 r-1 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 R-1 R-1 R-1 R-1 — R-0 MMU Size<5:0> R-1 R-0 R-0 R-1 IS<1:0> R-0 R-1 IS<2> R-0 IL<2:0> R-0 R-0 R-0 R-1 R-1 IA<2:0> R-1 DS<2:0> R-1 R-0 DL<2:0> R-1 DA<2:1> R-1 U-0 U-0 R-1 R-1 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-3: Bit Range 31:24 23:16 15:8 7:0 CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 r-1 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 R-1 R-0 R-0 R-0 R-1 R/W-y MCU ISAONEXC(1) — R-y IPLW<1:0> R-y ISA<1:0>(1) MMAR<2:0> R-1 R-1 R-1 R-1 U-0 R-1 ULRI RXI
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-4: Bit Range 31:24 23:16 15:8 7:0 CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-6: Bit Range 31:24 23:16 15:8 7:0 FIR: FLOATING POINT IMPLEMENTATION REGISTER; CP1 REGISTER 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 — — Bit 24/16/8/0 U-0 R-1 U-0 U-0 U-0 R-1 — UFRP — — — FC R-1 R-1 R-1 R-1 R-1 R-0 R-0 R-1 HAS2008 F64 L W MIPS3D PS D S R-1 R-0 R-1 R-0 R-0 R-1 R-1 R-1 R-x R-x R-x R-x R-x R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-7: Bit Range 31:24 23:16 15:8 FCCR: FLOATING POINT CONDITION CODES REGISTER; CP1 REGISTER 25 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-x R/W-x R/W-x
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-8: FEXR: FLOATING POINT EXCEPTIONS STATUS REGISTER; CP1 REGISTER 26 Bit Range 31:24 23:16 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x — — — — — — E V R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 — — — — R/W-x R/W-x U-0 U-0 U
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-9: FENR: FLOATING POINT EXCEPTIONS AND MODES ENABLE REGISTER; CP1 REGISTER 28 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — — — V Z
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-10: FCSR: FLOATING POINT CONTROL AND STATUS REGISTER; CP1 REGISTER 31 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R-0 R-1 R-1 R/W-x R/W-x 31:24 23:16 FCC<7:1> FCC<0> FO FN MAC2008 ABS2008 NAN2008 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 15:8 R/W-x
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-10: FCSR: FLOATING POINT CONTROL AND STATUS REGISTER; CP1 REGISTER 31 bit 16 V: Invalid Operation bit bit 15 Z: Divide-by-Zero bit bit 14 O: Overflow bit bit 13 U: Underflow bit bit 12 I: Inexact bit bit 11-7 ENABLES<4:0>: FPU Exception Enable bits These bits control whether or not a trap is taken when an IEEE exception condition occurs for any of the five conditions.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 4.0 Note: MEMORY ORGANIZATION 4.1 This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source.For detailed information, refer to Section 48. “Memory Organization and Permissions” in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY(1,2) 0xD4000000 0xD3FFFFFF 0xD0000000 0xC4000000 0xC3FFFFFF 0xC0000000 0xBFFFFFFF 0xBFC74000 0xBFC73FFF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Reserved Reserved External Memory via SQI Reserved External Memory via EBI KSEG3(4) (not cacheable) 0xE4000000 0xE3FFFFFF 0xE0000000 Physical Memory Map External Memory via SQI Reserved Reserved External Memory vi
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND 256 KB OF RAM(1,2) 0xD4000000 0xD3FFFFFF 0xD0000000 0xC4000000 0xC3FFFFFF 0xC0000000 0xBFFFFFFF 0xBFC74000 0xBFC73FFF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 Reserved Reserved External Memory via SQI Reserved External Memory via EBI KSEG3(4) (not cacheable) 0xE4000000 0xE3FFFFFF 0xE0000000 Physical Memory Map External Memory via SQI Reserved Reserved External Memory via S
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND 512 KB OF RAM(1,2) 0xD4000000 0xD3FFFFFF 0xD0000000 0xC4000000 0xC3FFFFFF 0xC0000000 0xBFFFFFFF 0xBFC74000 0xBFC73FFF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD0FFFFF Reserved Reserved External Memory via SQI Reserved External Memory via EBI KSEG3(4) (not cacheable) 0xE4000000 0xE3FFFFFF 0xE0000000 Physical Memory Map External Memory via SQI Reserved Reserved
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family MEMORY MAP FOR DEVICES WITH 2048 KB OF PROGRAM MEMORY(1,2) 0xD4000000 0xD3FFFFFF 0xD0000000 0xC4000000 0xC3FFFFFF 0xC0000000 0xBFFFFFFF 0xBFC74000 0xBFC73FFF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 Reserved Reserved External Memory via SQI Reserved External Memory via EBI KSEG3(4) (not cacheable) 0xE4000000 0xE3FFFFFF 0xE0000000 Physical Memory Map External Memory via SQI Reserved Reserved External Memory via SQI Reserved Exter
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 4-5: BOOT AND ALIAS MEMORY MAP SFR MEMORY MAP Virtual Address Peripheral Physical Memory Map(1) 0x1FC74000 Sequence/Configuration Space(3) 0x1FC70000 0x1FC6FF00 Boot Flash 2 0x1FC60000 Reserved Serial TABLE 4-1: 0x1FC54020 Number(4) 0x1FC54000 Sequence/Configuration Space(3) 0x1FC50000 0x1FC4FF00 System Bus(1) 0x1FC40000 0x1FC34000 (5) 0x1FC30000 0x1FC2FF00 Upper Boot Alias 0x1FC20000 EBI 0x1000 SQI1 0xBF8E0000
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 4.1.1 BOOT FLASH SEQUENCE AND CONFIGURATION SPACES 4.1.2 Sequence space is used to identify which boot Flash is aliased by aliased regions. If the value programmed into the TSEQ<15:0> bits of the BF1SEQ0 word is equal to or greater than the value programmed into the TSEQ<15:0> bits of the BF2SEQ0 word, Boot Flash 1 is aliased by the lower boot alias region, and Boot Flash 2 is aliased by the upper boot alias region.
BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY ABF1DEVCFG3 ABF1DEVCFG2 ABF1DEVCFG1 ABF1DEVCFG0 ABF1DEVCP3 ABF1DEVCP2 ABF1DEVCP1 ABF1DEVCP0 ABF1DEVSIGN3 ABF1DEVSIGN2 ABF1DEVSIGN1 ABF1DEVSIGN0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 Preliminary 2015 Microchip Technology Inc. 31:0 31:0 31:0 31:0 31:0 31:0 Note: See Table 34-2 for the bit descriptions.
BOOT FLASH 2 SEQUENCE AND CONFIGURATION WORDS SUMMARY ABF2DEVCFG3 ABF2DEVCFG2 ABF2DEVCFG1 ABF2DEVCFG0 ABF2DEVCP3 ABF2DEVCP2 ABF2DEVCP1 ABF2DEVCP0 ABF2DEVSIGN3 ABF2DEVSIGN2 ABF2DEVSIGN1 ABF2DEVSIGN0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 Preliminary DS60001320B-page 69 31:0 31:0 31:0 31:0 31:0 31:0 Note: See Table 34-2 for the bit descriptions.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-1: Bit Range 31:24 23:16 15:8 7:0 BFxSEQ0/ABFxSEQ0: BOOT FLASH ‘x’ SEQUENCE WORD 0 REGISTER (‘x’ = 1 AND 2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P CSEQ<15:8> R/P R/P R/P R/P R/P R/P R/P R/P CSEQ<7:0> TSEQ<15:8> R/P R/P R/P R/P R/P TSEQ
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 4.2 Note: System Bus Arbitration The System Bus interconnect implements one or more instantiations of the SonicsSX® interconnect from Sonics, Inc. This document contains materials that are (c) 2003-2015 Sonics, Inc., and that constitute proprietary information of Sonics, Inc. SonicsSX is a registered trademark of Sonics, Inc. All such materials and trademarks are used under license from Sonics, Inc.
INITIATORS TO TARGETS ACCESS ASSOCIATION Initiator ID Target # 2 3 4 CPU DMA Read Flash Memory: Program Flash Boot Flash Prefetch Module X X 2 RAM Bank 1 Memory X X 3 RAM Bank 2 Memory X X 4 External Memory via EBI and EBI Module X 5 Peripheral Set 1: System Control, Flash Control, DMT, RTCC, CVR, PPS Input, PPS Output, Interrupts, DMA, WDT X Peripheral Set 2: SPI1-SPI6 I2C1-I2C5 UART1-UART6 PMP 1 Name 1 5 6 DMA Write 7 USB 8 9 Ethernet Ethernet Read Write 10 11
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The System Bus arbitration scheme implements a nonprogrammable, Least Recently Serviced (LRS) priority, which provides Quality Of Service (QOS) for most initiators. However, some initiators can use Fixed High Priority (HIGH) arbitration to guarantee their access to data. 4.3 The arbitration scheme for the available initiators is shown in Table 4-5.
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS SBTxREGy Register Target Number Target Description (5) Name System Bus 0 SBT0REG0 SBT0REG1 Flash Memory(6): Program Flash Boot Flash Prefetch Module 1 Preliminary RAM Bank 1 Memory 2 RAM Bank 2 Memory 3 2015 Microchip Technology Inc.
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED) SBTxREGy Register Target Number 6 7 8 Preliminary 9 10 11 12 13 Legend: Note 1: 2: 3: 4: 5: 6: Target Description(5) Peripheral Set 5: CAN1 CAN2 Ethernet Controller Peripheral Set 6: USB External Memory via SQI1 and SQI1 Module Read Permission (GROUP3, GROUP2, GROUP1, GROUP0) SBTxWRy Register Write Permission (GROUP3, GROUP2, GROUP1, GROUP0) Region Base (BASE<21:0>) (see Note 2) Physical Start Address Region Size (SIZE<4:0>) (
Virtual Address (BF8F_#) Register Name 0510 SBFLAG 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 — — — — — — — — — 15:0 — — T13PGV T12PGV T11PGV T10PGV T9PGV T8PGV T7PGV x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Virtual Address (BF8F_#) Register Name 8420 SBT1ELOG1 8424 SBT1ELOG2 8428 SBT1ECON 8430 SBT1ECLRS SBT1REG0 Preliminary 8450 SBT1RD0 8458 SBT1WR0 8480 SBT1REG2 8490 SBT1RD2 8498 SBT1WR2 84A0 SBT1REG3 DS60001320B-page 77 84B0 SBT1RD3 84B8 SBT1WR3 84C0 SBT1REG4 84D0 SBT1RD4 84D8 SBT1WR4 Legend: Note: 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — REGION<3:0> — 1
Virtual Address (BF8F_#) Register Name 84E0 SBT1REG5 SYSTEM BUS TARGET 1 REGISTER MAP (CONTINUED) 84F0 SBT1RD5 84F8 SBT1WR5 8500 SBT1REG6 Preliminary 8510 SBT1RD6 8518 SBT1WR6 8520 SBT1REG7 8530 SBT1RD7 8538 SBT1WR7 8540 SBT1REG8 8550 SBT1RD8 8558 SBT1WR8 Legend: Note: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 PRI — 31:16 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — xxxx — — — xxxx BASE<21:6> 15:0 BASE<5:0> xxxx SIZE<4:0> 31:16 — — — — —
8824 8828 8830 SBT2ELOG2 SBT2ECON SBT2ECLRS 8838 SBT2ECLRM 8840 SBT2REG0 Preliminary 8850 SBT2RD0 8858 SBT2WR0 8860 SBT2REG1 8870 SBT2RD1 8878 SBT2WR1 8880 SBT2REG2 DS60001320B-page 79 8890 SBT2RD2 8898 SBT2WR2 Legend: Note: Bits 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — REGION<3:0> — 17/1 16/0 — — CMD<2:0> All Resets Register Name SBT2ELOG1 Bit Range V
8C24 SBT3ELOG2 8C28 SBT3ECON 8C30 SBT3ECLRS 8C38 SBT3ECLRM 8C40 SBT3REG0 Preliminary 8C50 SBT3RD0 8C58 SBT3WR0 8C60 SBT3REG1 8C70 SBT3RD1 8C78 SBT3WR1 8C80 SBT3REG2 2015 Microchip Technology Inc.
9024 9028 9030 SBT4ELOG2 SBT4ECON SBT4ECLRS 9038 SBT4ECLRM 9040 SBT4REG0 Preliminary 9050 SBT4RD0 9058 SBT4WR0 9080 SBT4REG2 9090 SBT4RD2 9098 SBT4WR2 Legend: Note: Bits 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — REGION<3:0> — 17/1 16/0 — — CMD<2:0> All Resets Register Name SBT4ELOG1 Bit Range Virtual Address (BF8F_#) 9020 SYSTEM BUS TARGET 4 REGISTER MAP 000
9424 9428 9430 SBT5ELOG2 SBT5ECON SBT5ECLRS 9438 SBT5ECLRM 9440 SBT5REG0 Preliminary 9450 SBT5RD0 9458 SBT5WR0 9460 SBT5REG1 9470 SBT5RD1 9478 SBT5WR1 9480 SBT5REG2 2015 Microchip Technology Inc.
9824 9828 9830 SBT6ELOG2 SBT6ECON SBT6ECLRS 9838 SBT6ECLRM 9840 SBT6REG0 Preliminary 9850 SBT6RD0 9858 SBT6WR0 9860 SBT6REG1 9870 SBT6RD1 9878 SBT6WR1 Legend: Note: Bits 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — REGION<3:0> — 17/1 16/0 — — CMD<2:0> All Resets Register Name SBT6ELOG1 Bit Range Virtual Address (BF8F_#) 9820 SYSTEM BUS TARGET 6 REGISTER MAP 000
9C24 SBT7ELOG2 9C28 SBT7ECON 9C30 SBT7ECLRS 9C38 SBT7ECLRM 9C40 SBT7REG0 Preliminary 9C50 SBT7RD0 9C58 SBT7WR0 9C60 SBT7REG1 9C70 SBT7RD1 9C78 SBT7WR1 2015 Microchip Technology Inc.
A024 SBT8ELOG2 A028 SBT8ECON A030 SBT8ECLRS A038 SBT8ECLRM A040 SBT8REG0 Preliminary A050 SBT8RD0 A058 SBT8WR0 A060 SBT8REG1 A070 SBT8RD1 A078 SBT8WR1 Legend: Note: Bits 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — REGION<3:0> — 17/1 16/0 — — CMD<2:0> All Resets Bit Range Register Name Virtual Address (BF8F_#) A020 SBT8ELOG1 SYSTEM BUS TARGET 8 REGISTER MAP 0000
A424 SBT9ELOG2 A428 SBT9ECON A430 SBT9ECLRS A438 SBT9ECLRM A440 SBT9REG0 Preliminary A450 SBT9RD0 A458 SBT9WR0 A460 SBT9REG1 A470 SBT9RD1 A478 SBT9WR1 2015 Microchip Technology Inc.
A824 SBT10ELOG2 A828 SBT10ECON A830 SBT10ECLRS A838 SBT10ECLRM A840 SBT10REG0 Preliminary A850 SBT10RD0 A858 SBT10WR0 Legend: Note: Bits 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — REGION<3:0> — 17/1 16/0 — — CMD<2:0> All Resets Bit Range Register Name Virtual Address (BF8F_#) A820 SBT10ELOG1 SYSTEM BUS TARGET 10 REGISTER MAP 0000 0000 31:16 — — — — — — — —
AC24 SBT11ELOG2 AC28 SBT11ECON AC30 SBT11ECLRS AC38 SBT11ECLRM AC40 SBT11REG0 Preliminary AC50 SBT11RD0 AC58 SBT11WR0 AC60 SBT11REG1 AC70 SBT11RD1 AC78 SBT11WR1 2015 Microchip Technology Inc.
B024 SBT12ELOG2 B028 SBT12ECON B030 SBT12ECLRS B038 SBT12ECLRM B040 SBT12REG0 Preliminary B050 SBT12RD0 B058 SBT12WR0 Legend: Note: Bits 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — — REGION<3:0> 17/1 16/0 — — CMD<2:0> All Resets Bit Range Register Name Virtual Address (BF8F_#) B020 SBT12ELOG1 SYSTEM BUS TARGET 12 REGISTER MAP 0000 0000 31:16 — — — — — — — —
B424 SBT13ELOG2 B428 SBT13ECON B430 SBT13ECLRS B438 SBT13ECLRM B440 SBT13REG0 Preliminary B450 SBT13RD0 B458 SBT13WR0 Legend: Note: Bits 31/15 31:16 MULTI 30/14 29/13 28/12 — — — 15:0 27/11 26/10 25/9 24/8 CODE<3:0> 23/7 — INITID<7:0> 22/6 21/5 20/4 19/3 18/2 — — — — — — REGION<3:0> 17/1 16/0 — — CMD<2:0> All Resets Bit Range Register Name Virtual Address (BF8F_#) B420 SBT13ELOG1 SYSTEM BUS TARGET 13 REGISTER MAP 0000 0000 31:16 — — — — — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-2: Bit Range 31:24 23:16 15:8 7:0 SBFLAG: SYSTEM BUS STATUS FLAG REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — T13PGV T12PGV T11PGV T10PGV T9PGV T8PGV R-0 R-0 R-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-3: Bit Range SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1 (‘x’ = 0-13) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0, C U-0 U-0 U-0 R/W-0, C R/W-0, C R/W-0, C R/W-0, C U-0 U-0 31:24 23:16 15:8 MULTI — — — U-0 U-0 U-0 U-0 CODE<3:0> U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-3: bit 7-4 bit 3 bit 2-0 Note: SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1 (‘x’ = 0-13) (CONTINUED) REGION<3:0>: Requested Region Number bits 1111 - 0000 = Target’s region that reported a permission group violation Unimplemented: Read as ‘0’ CMD<2:0>: Transaction Command of the Requester bits 111 = Reserved 110 = Reserved 101 = Write (a non-posted write) 100 = Reserved 011 = Read (a locked read caused by a Read-Modi
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-4: Bit Range 31:24 23:16 15:8 7:0 SBTxELOG2: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 2 (‘x’ = 0-13) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-6: Bit Range 31:24 23:16 15:8 7:0 SBTxECLRS: SYSTEM BUS TARGET ‘x’ SINGLE ERROR CLEAR REGISTER (‘x’ = 0-13) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-8: Bit Range 31:24 23:16 15:8 7:0 SBTxREGy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ REGISTER (‘x’ = 0-13; ‘y’ = 0-8) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 U-0 BASE<21:14> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BASE<13:6> R/W-0 R/W-0 BASE<5:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-9: Bit Range 31:24 23:16 15:8 7:0 SBTxRDy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ READ PERMISSIONS REGISTER (‘x’ = 0-13; ‘y’ = 0-8) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 4-10: Bit Range 31:24 23:16 15:8 7:0 SBTxWRy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ WRITE PERMISSIONS REGISTER (‘x’ = 0-13; ‘y’ = 0-8) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 52. “Flash Program Memory with Support for Live Update” (DS60001193) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Flash Control Registers Register Name FLASH CONTROLLER REGISTER MAP Virtual Address (BF80_#) TABLE 5-1: 0600 NVMCON(1) 0610 NVMKEY (1) 0620 NVMADDR 0630 0640 0650 NVMDATA0 NVMDATA1 NVMDATA2 Preliminary 0660 NVMDATA3 0670 NVMSRC ADDR 0680 0690 (1) NVMPWP (1) NVMBWP 06A0 NVMCON2(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — 31:16 — — — — — — — — — — — — 15:0 WR WREN WRERR LVDERR — — — — PFSWAP B
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-1: Bit Range 31:24 23:16 15:8 7:0 NVMCON: FLASH PROGRAMMING CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — R/W-0, HC (1) WR — R/W-0 (1) WREN — — — — — — R-0, HS, HC (1) R-0, HS, HC (1) U-0 U-0 U-0 U-0 — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-1: NVMCON: FLASH PROGRAMMING CONTROL REGISTER (CONTINUED) bit 6 BFSWAP: Boot Flash Bank Alias Swap Control bit This bit is only writable when WREN = 0 and the unlock sequence has been performed.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMCON2: FLASH PROGRAMMING CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-3: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Note: W-0 31:24 23:16 15:8 7:0 W-0 W-0 W-0 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-5: Bit Range 31:24 23:16 15:8 7:0 NVMDATAx: FLASH DATA REGISTER (x = 0-3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<23:16> R/W-0 NVMDATA<15:8>
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-7: Bit Range 31:24 23:16 15:8 7:0 NVMPWP: PROGRAM FLASH WRITE-PROTECT REGISTER Bit 31/23/15/7 Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 PWPULOCK — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWP<23:16> R-0 R-0 PWP<15:8> R-0 R-0 R-0 R-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-8: Bit Range 31:24 23:16 15:8 7:0 NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER Bit 31/23/15/7 Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 LBWPULOCK — — LBWP4(1) LBWP3(1) LBWP2(1)
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 5-8: NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER bit 4 UBWP4: Upper Boot Alias Page 4 Write-protect bit(1) 1 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF enabled 0 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF disabled bit 3 UBWP3: Upper Boot Alias Page 3 Write-protect bit(1) 1 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF enabled 0 = Write protect
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 6.0 Note: RESETS This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS60001118) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Reset Control Registers Virtual Address (BF80_#) Register Name TABLE 6-1: 1240 RCON 1250 1260 1270 RESETS REGISTER MAP RSWRST RNMICON PWRCON Legend: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — — — — 15:0 — — — — 25/9 24/8 — — — — — — — — — — — — 0x00 CMR — EXTR SWR DMTO WDTO SLEEP IDLE BOR POR 31:16 — — — — — — 0003 — — — — — — — — — — 15:0 — — — — — 0000 — — — — — — — — — — SWRST 31:16 — — — — — 0000 — DMTO WDTO
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 6-1: Bit Range 31:24 23:16 15:8 7:0 RCON: RESET CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — R/W-0, HS R/W-0, HS U-0 U-0 BCFGERR BCFGFAIL — U-0 U-0 U-0 U-0 U-0 — U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS U-0 — — — — — — CMR — R/W-0, HS R/W-0, H
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 — — U-0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 6-3: Bit Range 31:24 23:16 15:8 7:0 RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — DMTO WDTO R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 SWNMI — — — GNMI — CF WDTS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 6-4: Bit Range 31:24 23:16 15:8 7:0 PWRCON: POWER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 — — U-0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 7.0 Note: CPU EXCEPTIONS AND INTERRUPT CONTROLLER The CPU handles interrupt events as part of the exception handling mechanism, which is described in Section 7.1 “CPU Exceptions”. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupt Controller” (DS60001108) and Section 50.
CPU Exceptions CPU coprocessor 0 contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data, external events or program errors. Table 7-1 lists the exception types in order of priority.
Exception Type (In Order of Priority) IBE Instruction Validity Exceptions Execute Exception Tr DDBL/DDBS Preliminary WATCH AdEL AdES TLBL TLBS DBE DDBL CBrk MIPS32® M-CLASS MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED) DS60001320B-page 117 Description Branches to Status Bits Set Debug Bits Set Instruction fetch bus error. An instruction could not be completed because it was not allowed to access the required resources (Coprocessor Unusable) or was illegal (Reserved Instruction).
Interrupts For details on the Variable Offset feature, refer to 8.5.2 “Variable Offset” in Section 8. “Interrupt Controller” (DS60001108) of the “PIC32 Family Reference Manual”. The PIC32MZ EF family uses variable offsets for vector spacing. This allows the interrupt vector spacing to be configured according to application needs. A unique interrupt vector offset can be set for each vector using its associated OFFx register.
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Interrupt Bit Location Sub-priority Persistent Interrupt Vector # Flag Enable Priority Preliminary DS60001320B-page 119 Output Compare 4 _OUTPUT_COMPARE_4_VECTOR 22 OFF022<17:1> IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16> No External Interrupt 4 _EXTERNAL_4_VECTOR 23 OFF023<17:1> IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24> No Timer5 _TIMER_5_VECTOR 24 OFF024<17:1> IFS0<24> IEC0<24> IPC6<4:2> IPC
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Interrupt Bit Location Persistent Sub-priority Interrupt Vector # Flag Enable Priority Preliminary 2015 Microchip Technology Inc.
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Interrupt Bit Location Vector # Flag Enable Priority Sub-priority Persistent Interrupt ADC Data 19(2) _ADC_DATA19_VECTOR 78 OFF078<17:1> IFS2<14> IEC2<14> IPC19<20:18> IPC19<17:16> Yes ADC Data 20(2) _ADC_DATA20_VECTOR 79 OFF079<17:1> IFS2<15> IEC2<15> IPC19<28:26> IPC19<25:24> Yes (2) _ADC_DATA21_VECTOR 80 OFF080<17:1> IFS2<16> IEC2<16> IPC20<4:2> IPC20<1:0> Yes ADC Data 22(2) _ADC_DATA22_V
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Interrupt Bit Location Persistent Sub-priority Interrupt Vector # Flag Enable Priority System Bus Protection Violation _SYSTEM_BUS_PROTECTION_VECTOR 106 OFF106<17:1> IFS3<10> IEC3<10> IPC26<20:18> IPC26<17:16> Yes Crypto Engine Event _CRYPTO_VECTOR Yes Reserved — 107 OFF107<17:1> IFS3<11> IEC3<11> IPC26<28:26> IPC26<25:24> 108 — — — — — — SPI1 Fault _SPI1_FAULT_VECTOR 109 OFF109<17:1> IFS
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Interrupt Bit Location Vector # Flag Enable Priority Sub-priority Persistent Interrupt Preliminary DMA Channel 0 _DMA0_VECTOR 134 OFF134<17:1> IFS4<6> IEC4<6> IPC33<20:18> IPC33<17:16> No DMA Channel 1 _DMA1_VECTOR 135 OFF135<17:1> IFS4<7> IEC4<7> IPC33<28:26> IPC33<25:24> No DMA Channel 2 _DMA2_VECTOR 136 OFF136<17:1> IFS4<8> IEC4<8> IPC34<4:2> IPC34<1:0> No DMA Channel 3 _DMA3_VECTOR 137
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Interrupt Bit Location Persistent Sub-priority Interrupt Vector # Flag Enable Priority Preliminary I2C3 Master Event _I2C3_MASTER_VECTOR 162 OFF162<17:1> IFS5<2> IEC5<2> IPC40<20:18> IPC40<17:16> Yes SPI4 Fault _SPI4_FAULT_VECTOR 163 OFF163<17:1> IFS5<3> IEC5<3> IPC40<28:26> IPC40<25:24> Yes SPI4 Receive Done _SPI4_RX_VECTOR 164 OFF164<17:1> IFS5<4> IEC5<4> IPC41<4:2> IPC41<1:0> Yes SPI4 Tra
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) UART6 Transfer Done Reserved XC32 Vector Name _UART6_TX_VECTOR — IRQ # Interrupt Bit Location Vector # Flag Enable Priority Sub-priority 190 OFF190<17:1> IFS5<30> IEC5<30> IPC47<20:18> IPC47<17:16> 191 — — — — — IPC48<4:2> IPC48<1:0> Yes IPC48<9:8> Yes _ADC_EOS_VECTOR 192 OFF192<17:1> IFS6<0> IEC6<0> ADC Analog Circuits Ready _ADC_ARDY_VECTOR 193 OFF193<17:1> IFS6<1> IEC6<1> IPC48<12:10> ADC Update Ready _ADC_UR
Interrupt Control Registers 0000 INTCON 0010 PRISS 0020 INTSTAT 0030 IPTMR 0040 IFS0 Preliminary (6) 0080 IFS4 0090 IFS5 00A0 IFS6 29/13 28/12 — — — MVEC 31:16 15:0 2015 Microchip Technology Inc.
0100 IEC4 0110 IEC5 0120 IEC6 0140 IPC0 0150 IPC1 Preliminary 0160 IPC2 0170 IPC3 0180 IPC4 0190 IPC5 01A0 IPC6 01B0 IPC7 01C0 IPC8 01D0 IPC9 01E0 IPC10 DS60001320B-page 127 Legend: Note Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE 18/2 16/0 U1RXIE U1EIE 31:16 CNKIE CNJIE CNHIE CNGIE CNFIE CNEIE CNDIE CNCIE 15:0 SPI1TXIE SPI1RXIE SPI1EIE — CRPTIE(7) SBIE CFDCIE CPCIE 31:16 U3TXIE U3
0200 IPC12 0210 IPC13 0220 IPC14 0230 IPC15 0240 IPC16 Preliminary 0250 IPC17 0260 IPC18 0270 IPC19 0280 IPC20 0290 IPC21 02A0 IPC22 02B0 IPC23 2015 Microchip Technology Inc.
02F0 IPC27 0300 IPC28 0310 IPC29 0320 IPC30 0330 IPC31 Preliminary 0340 IPC32 0350 IPC33 0360 IPC34 0370 IPC35 0380 IPC36 0390 IPC37 03A0 IPC38 03B0 IPC39 03C0 IPC40 DS60001320B-page 129 Legend: Note Bits 31/15 30/14 29/13 28/12 27/11 31:16 — — — CRPTIP<2:0>(7) 15:0 — — — CFDCIP<2:0> 31:16 — — — 15:0 — — 31:16 — 15:0 26/10 25/9 24/8 20/4 23/7 22/6 21/5 CRPTIS<1:0>(7) — — — SBIP<2:0> SBIS<1:0> 0000 CFDCIS<1:0> — — — CPCIP<2:0> CPCIS<1:0> 0000 SP
03E0 IPC42 03F0 IPC43 0400 IPC44 0410 IPC45 0420 IPC46 Preliminary 0430 IPC47 0440 IPC48 0450 IPC49 0460 IPC50 0470 IPC51 0480 IPC52 0490 IPC53 2015 Microchip Technology Inc.
054C OFF003 0550 OFF004 0554 OFF005 0558 OFF006 055C OFF007 Preliminary 0560 OFF008 0564 OFF009 0568 OFF010 056C OFF011 0570 OFF012 0574 OFF013 0578 OFF014 057C OFF015 0580 OFF016 DS60001320B-page 131 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — —
0588 OFF018 058C OFF019 0590 OFF020 0594 OFF021 0598 OFF022 Preliminary 059C OFF023 05A0 OFF024 05A4 OFF025 05A8 OFF026 05AC OFF027 05B0 OFF028 05B4 OFF029 2015 Microchip Technology Inc.
05C4 OFF033 05C8 OFF034 05CC OFF035 05D0 OFF036 05D4 OFF037 Preliminary 05D8 OFF038 05DC OFF039 05E0 OFF040 05E4 OFF041 05E8 OFF042 05EC OFF043 05F0 OFF044 05F4 OFF045 05F8 OFF046 DS60001320B-page 133 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — —
0600 OFF048 0604 OFF049 0608 OFF050 060C OFF051 0610 OFF052 Preliminary 0614 OFF053 0618 OFF054 061C OFF055 0620 OFF056 0624 OFF057 0628 OFF058 062C OFF059 2015 Microchip Technology Inc.
063C OFF063 0640 OFF064 0644 OFF065 0648 OFF066 064C OFF067 Preliminary 0650 OFF068 0654 OFF069 0658 OFF070 065C OFF071 0660 OFF072 0664 OFF073 0668 OFF074 066C OFF075 0670 OFF076 DS60001320B-page 135 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — —
0678 OFF078 (2) 0680 OFF080 (2) 0684 OFF081 (2) (2) Preliminary (2) 27/11 26/10 25/9 — — — — — — — 15:0 31:16 31:16 31:16 31:16 — — — — — — — 31:16 — — — — — — 06A0 OFF088 (2) 06A4 OFF089 (2) 31:16 — — — — — — — — — — — — 2015 Microchip Technology Inc.
06B4 OFF093(2) 06B8 OFF094 (2,4) 06BC OFF095 (2,4) Preliminary 06C8 OFF098(2,4) 06CC OFF099 (2,4) 06D0 OFF100 (2,4) 06E0 OFF104 06E4 OFF105 06E8 OFF106 DS60001320B-page 137 Legend: Note 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 31:16 31:16 — — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
31:16 31:16 27/11 26/10 25/9 — — — — — — — 31:16 — — — — — — — Preliminary 070C OFF115 — — — — — — 0710 OFF116 0714 OFF117 — — — — — — 0718 OFF118(2) — — — — — — — — — — — — 2015 Microchip Technology Inc.
31:16 0734 OFF125 0738 OFF126 (2,4) Preliminary 0750 OFF132 0754 OFF133 0758 OFF134 075C OFF135 0760 OFF136 0764 OFF137 DS60001320B-page 139 Legend: Note 29/13 28/12 27/11 26/10 25/9 — — — — — — — 31:16 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
31:16 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 31:16 0774 OFF141 — — — — — — — 0778 OFF142 — — — — — — 077C OFF143 Preliminary 0780 OFF144 — — — — — — 0784 OFF145 0788 OFF146 — — — — — — 078C OFF147 0790 OFF148(2) 0794 OFF149 (2) — — — — — — 0798 OFF150 (2) — — — — — — 2015 Microchip Technology Inc.
07A8 OFF154 07AC OFF155 07B0 OFF156 07B4 OFF157 07B8 OFF158 Preliminary 07BC OFF159 07C0 OFF160 07C4 OFF161 07C8 OFF162 07CC OFF163 07D0 OFF164 07D4 OFF165 07D8 OFF166 07DC OFF167 DS60001320B-page 141 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — —
31:16 31:16 31:16 31:16 31:16 26/10 25/9 — — — — — — — 31:16 Preliminary 07FC OFF175 — — — — — — — 0800 OFF176(2) (2) — — — — — — 0808 OFF178(2) — — — — — — — — — — — — 2015 Microchip Technology Inc.
31:16 0824 OFF185 0828 OFF186 (2) Preliminary 0844 OFF193 0848 OFF194 0850 OFF196 0858 OFF198 085C OFF199 0860 OFF200 DS60001320B-page 143 Legend: Note 29/13 28/12 27/11 26/10 25/9 — — — — — — — 31:16 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
0868 OFF202 0874 OFF205 0878 OFF206 087C OFF207 0880 OFF208 Preliminary 0884 OFF209 0888 OFF210 0894 OFF213 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF<15:1> VOFF<17:16> VOFF<17:16>
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 U-0 NMIKEY<7:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — MVEC — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-2: Bit Range PRISS: PRIORITY SHADOW SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 31:24 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 PRI7SS<3:0>(1) R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRI2SS<3:0>(1) R/W-0 R/W-0 PRI1SS<3:0>(1) Legend: R = Readable bit -n = Value at POR
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED) bit 15-12 PRI3SS<3:0>: Interrupt with Priority Level 3 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0) 0111 = Interrupt with a priority level of 3 uses Shadow Set 7 0110 = Interrupt with a priority level of 3 uses Shadow Set 6 • • • bit 11-8 0001 = Interrupt with a priority level of 3 uses Shadow Set 1 0000 = Interr
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-3: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — R-0 R-0 R-0 R-0 SRIPL<2:0>(1) R-0 R-0 R-0 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-5: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-7: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP3<2:0> R/W-0 R/W-0 IS3<1:0> R/W-0 IP2<2:0> R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) bit 12-10 IP1<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 9-8 bit 7-5 bit 4-2 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS1<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-8: Bit Range 31:24 23:16 15:8 7:0 OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-190) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 R/W-0 R/W-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VOFF<17:16> R/W-0 R/W-0 R/W-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320B-page 154 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 8.0 Note: OSCILLATOR CONFIGURATION The PIC32MZ EF oscillator system has the following modules and features: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 8-1: PIC32MZ EF FAMILY OSCILLATOR DIAGRAM (12 or 24 MHz only) From POSC USB Clock (USBCLK) USB PLL Reference Clock(5) REFCLKIx POSC FRC LPRC SOSC PBCLK1 SYSCLK BFRC System PLL N REFOxTRIM REFOxCON UPLLFSEL FVco(6) FIN(6) PLL x M PLLODIV<2:0> (N) PLLIDIV<2:0> PLLRANGE<2:0> (N) PLLMULT<6:0> PLLICLK (M) N FPLL(6) ROTRIM<8:0> (M) OE M 2 N + --------512 RODIV<14:0> (N) REFCLKOx FREF(6) To SPI, ADC, SQI ‘x’ =
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 8-1: SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION CPU X WDT X X(2) Deadman Timer X(2) X (2) (2) Flash X X X(2) ADC X X X(3) Comparator X Crypto X RNG X USB X X(3) CAN X Ethernet X(3) PMP X 2 I C™ X UART X RTCC X X X(2) EBI X (3) SQI X X SPI X X Timers X(4) X Output Compare X Input Capture X Ports X DMA X Interrupts X Prefetch X OSC2 Pin X(5) Note 1: PBCLK1 is used by system modules and cannot be turned off.
Oscillator Control Registers Register Name(1) 1200 OSCCON 1210 OSCTUN 1220 OSCILLATOR CONFIGURATION REGISTER MAP SPLLCON 1280 REFO1CON 1290 REFO1TRIM 12A0 REFO2CON Preliminary 12B0 REFO2TRIM 12C0 REFO3CON 12D0 REFO3TRIM 12E0 REFO4CON 12F0 REFO4TRIM 1300 PB1DIV 2015 Microchip Technology Inc.
Register Name(1) PB7DIV 1370 13C0 13D0 PB8DIV SLEWCON CLKSTAT Bit Range Bits 31/15 30/14 29/13 28/12 31:16 — — — 15:0 ON — — 31:16 — — 15:0 ON 31:16 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 — — — — — — — — — — PBDIVRDY — — — — — — — — — — — — — — PBDIVRDY — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — UPEN DNEN BUSY 0204 31:16 — — — — — — — — — — — — — 0000 — LPRC RDY SOSC RDY — POSC RDY
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 OSCCON: OSCILLATOR CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 U-0 R/W-y U-0 U-0 DRMEN — U-0 R-0 — SLP2SPD (1) R-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 FRCDIV<2:0> U-0 U-0 U-0 — — — — — R-0 U-0 R/W-y R/W-y R/W-y COSC<2:0> — NOSC<2:0> R/W-0 U-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-1: bit 10-8 bit 7 OSCCON: OSCILLATOR CONTROL REGISTER NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV) 110 = Reserved 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Reserved 010 = Primary Oscillator (POSC) (HS or EC) 001 = System PLL (SPLL) 000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV) On Re
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-3: Bit Range 31:24 23:16 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R/W-y R/W-y R/W-y — — — — — U-0 R/W-y R/W-y R/W-y R/W-y U-0 U-0 U-0 R/W-y U-0 U-0 7:0 PLLICLK — — PLLODIV<2:0> R/W-y R/W-y R/W-y U-0 R/W-y R/W-y R/W-y U-0 U-0 R/W-y — — — U-0 15:8 SPLLCON: SYSTEM PLL CONTROL REGISTER P
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-3: bit 10-8 SPLLCON: SYSTEM PLL CONTROL REGISTER PLLIDIV<2:0>: System PLL Input Clock Divider bits 111 = Divide by 8 110 = Divide by 7 101 = Divide by 6 100 = Divide by 5 011 = Divide by 4 010 = Divide by 3 001 = Divide by 2 000 = Divide by 1 The default setting is specified by the FPLLIDIV<2:0> Configuration bits in the DEVCFG2 register.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-4: Bit Range REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (‘x’ = 1-4) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 R/W-0 R/W-0 R/W-0 31:24 — Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RODIV<14:8> R/W-0 23:16 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 RODIV<7:0> 15:8 7:0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC ON(1) —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-5: Bit Range 31:24 23:16 15:8 7:0 REFOxTRIM: REFERENCE OSCILLATOR TRIM REGISTER (‘x’ = 1-4) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ROTRIM<8:1> R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 ROTRIM<0> — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-6: Bit Range 31:24 23:16 15:8 7:0 PBxDIV: PERIPHERAL BUS ‘x’ CLOCK DIVISOR CONTROL REGISTER (‘x’ = 1-7) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 (1) U-0 U-0 U-0 R-1 U-0 U-0 U-0 — — — PBDIVRDY — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-7: Bit Range 31:24 23:16 15:8 7:0 SLEWCON: OSCILLATOR SLEW CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — U-0 U-0 U-0 U-0 SYSDIV<3:0>(1) U-0 R/W-0 R/W-1 R/W-0 — — — — — U-0 U-0 U-0 U-0 U-0 R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-8: Bit Range 31:24 23:16 15:8 7:0 CLKSTAT: OSCILLATOR CLOCK STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 U-0 R-0 R-0 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 170 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 9.0 PREFETCH MODULE Note: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 41. “Prefetch Module for Devices with L1 CPU Cache” (DS60001183) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Prefetch Control Registers Virtual Address (BF8E_#) Register Name(1) TABLE 9-1: 0000 PRECON 0010 PREFETCH REGISTER MAP PRESTAT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — — — — — PFMSECEN — — — — 15:0 — — — — — — — — — — 31:16 — — — — PFMDED PFMSEC — — — — 15:0 — — — — — — — — 21/5 20/4 19/3 18/2 — — — — PREFEN<1:0> — — — — PFMSECCNT<7:0> 17/1 16/0 — — PFMWS<2:0> — — All Resets Bit Range Bits 0000 0007 —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 9-1: Bit Range PRECON: PREFETCH MODULE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 31:24 23:16 15:8 7:0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 U-0 U-0 — — — — — PFMSECEN — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 U-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 PRESTAT: PREFETCH MODULE STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS U-0 U-0 — — — — PFMDED PFMSEC — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0, HS R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 10.0 Note: DIRECT MEMORY ACCESS (DMA) CONTROLLER This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS60001117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
DMA Control Registers Register Name(1) Bit Range DMA GLOBAL REGISTER MAP Virtual Address (BF81_#) TABLE 10-1: 1000 DMACON 31:16 15:0 — ON — — — — 1010 DMASTAT 31:16 15:0 RDWR — — — — — 1020 DMAADDR 31:16 15:0 29/13 28/12 27/11 — — SUSPEND DMABUSY — — — — 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — 0000 0000 — — — — — — — — — — — — — — — — — — DMACH<2:0> — 0000 0000 0000 0000 DMAADDR<31:0> DMA
Virtual Address (BF81_#) 1070 DCH0ECON DCH0INT 1090 DCH0SSA 10A0 DCH0DSA 10B0 DCH0SSIZ Preliminary 10C0 DCH0DSIZ 10D0 DCH0SPTR 10E0 DCH0DPTR 10F0 DCH0CSIZ 1100 DCH0CPTR 1110 DCH0DAT 1120 DCH1CON 1130 DCH1ECON DS60001320B-page 177 1140 DCH1INT 31/15 30/14 29/13 — — — CHPIGNEN — 31:16 — — — 15:0 — — — 31:16 27/11 26/10 25/9 24/8 23/7 — — — — — — — CHCHNS — CHEN CHAED CHCHN CHSIRQ<7:0> — — — — — — — — — CHPIGN<7:0> 15:0 CHBUSY 31:16 28/12 15:0 — — CHPATLEN —
Virtual Address (BF81_#) DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED) 1170 DCH1SSIZ 1180 DCH1DSIZ 1190 DCH1SPTR 11A0 DCH1DPTR 11B0 DCH1CSIZ 11C0 DCH1CPTR Preliminary 11D0 DCH1DAT 11E0 DCH2CON 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 19/3 18/2 17/1 16/0 — — — — — — — — — 0000 0000 — — — — — — CHDSIZ<15:0> — — — — — — — 0000 0000 — — — — — — — — — CHSPTR<15:0> — — — — — — — 0000 0000 — — — — — — —
Virtual Address (BF81_#) 1290 DCH2DAT 12A0 DCH3CON 12B0 DCH3ECON DCH3INT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — 0000 — — — — — — — 0000 — CHAED — CHCHN — CHAEN — — — CHEDET — — CHPRI<1:0> 0000 0000 PATEN CHAIRQ<7:0> SIRQEN AIRQEN — — 00FF FF00 CHCPTR<15:0> — — — — — — — 15:0 — — 0000 CHPDAT<15:0> 31:16 CHPIGN<7:0> 15:0 CHBUSY — CHPIGNEN 31:
Virtual Address (BF81_#) 13A0 DCH4DSA 13B0 DCH4SSIZ 13C0 DCH4DSIZ 13D0 DCH4SPTR 13E0 DCH4DPTR Preliminary 13F0 DCH4CSIZ 1400 DCH4CPTR 1410 DCH4DAT 1420 DCH5CON 1430 DCH5ECON DCH5INT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — — 15:0 31:16 — — — — — — — 21/5 20/4 19/3 18/2 17/1 16/0 0000 0000 0000 — — 0000 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — —
Virtual Address (BF81_#) 14B0 DCH5CSIZ 14C0 DCH5CPTR 14D0 DCH5DAT 14E0 DCH6CON 14F0 DCH6ECON Preliminary DCH6INT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — 15:0 31:16 — — — — — — — 15:0 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — CHAED — CHCHN — CHAEN — — — CHEDET — — CHPRI<1:0> 0000 0000 PATE
Virtual Address (BF81_#) DCH7INT 15D0 DCH7SSA 15E0 DCH7DSA 15F0 DCH7SSIZ 1600 DCH7DSIZ Preliminary 1610 DCH7SPTR 1620 DCH7DPTR 1630 DCH7CSIZ 1640 DCH7CPTR 1650 DCH7DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — — — — — — — 15:0 31:16 — — — CHSIRQ<7:0> — — 15:0 — — — — — 31:16 31:16 — — — — — — — 15:0 31:16 — — — — — — — 19/3 18/2 17/1 16/0 CHAIRQ<7:0> 00FF — CFORCE CABORT PATEN CHSDIE CHSHIE CHDDIE SIRQEN CHDHIE AIRQEN CHBCIE
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 ON — — SUSPEND DMABUSY — — — U-0 U-0 U-0 U-0 U
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 RDWR — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 — — U-0 U-0 U-0 — — — U-0 U-0 U-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 R/W-0 WBO(1) — — BITO U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BYTO<1:0> — — — R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 DCRCDATA<15:8> R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL x CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CHPIGN<7:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 CHBUSY — CHIPGNEN — CHPATLEN — — CHCHNS(1)
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-7: DCHxCON: DMA CHANNEL x CONTROL REGISTER (CONTINUED) bit 4 CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete bit 3 Unimplemented: Read as ‘0’ bit 2 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected bit 1-0 CHPRI<1:0>: Channel Priorit
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED) bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: C
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 31:24 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 198 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 11.0 HI-SPEED USB WITH ONTHE-GO (OTG) Note: The USB module includes the following features: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 51. “Hi-Speed USB with On-The-Go (OTG)” (DS60001326) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.
PIC32MZ EF FAMILY USB INTERFACE DIAGRAM USBCLK POSC (12 MHz or 24 MHz only) USB PLL UPLLFSEL Endpoint Control EP0 Control Host EPO Control Function DMA Requests Transmit EP1 - EP7 Control Combine Endpoints Receive Host Transaction Scheduler Interrupt Control Interrupts Preliminary EP Reg Decoder Common Regs D+ UTM Synchronization Packet Encode/Decode D- Data Sync Packet Encode HS Negotiation Packet Decode HNP/SRP CRC Gen/Check USBID VUSB3V3 VBUS USB 2.
USB OTG Control Registers USB REGISTER MAP 1 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — EP7TXIF EP6TXIF EP5TXIF EP4TXIF EP3TXIF EP2TXIF EP1TXIF EP0IF ISOUPD(1) SOFT CONN(1) —(2) —(2) —(2) —(2) —(2) 31:16 — — — — — 15:0 — — — — — SOFIE 31:16 3000 USBCSR0 3004 USBCSR1 3008 USBCSR2 300C USBCSR3 15:0 31/15 HSEN HSMODE 31:16 VBUSERRIE SESSRQIE DISCONIE CONNIE 15:0 — 31:16 FORCEHST 15:0 — — — FIFOAC
USB REGISTER MAP 1 (CONTINUED) Register Name Bit Range 3028 USB FIFO2 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 302C USB FIFO3 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 3030 USB FIFO4 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 3034 USB FIFO5 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 3038 USB FIFO6 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 303C USB FIFO7 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 3060 USBOTG 31/15 30/14 29/13 28/12 27/11 Preliminar
USB REGISTER MAP 1 (CONTINUED) 309C USB E3RXA 31:16 — 15:0 — 30A0 US BE4TXA 31:16 — 15:0 — 30A4 USB E4RXA 31:16 — 15:0 — 30A8 USB E5TXA 31:16 — 15:0 — 30AC USB E5RXA 31:16 — 15:0 — 30B0 USB E6TXA 31:16 — 15:0 — 30B4 USB E6RXA 31:16 — 15:0 — 30B8 USB E7TXA 31:16 — 15:0 — 30BC USB E7RXA 31:16 — 15:0 — 3100 USB E0CSR0 31:16 3108 USB E0CSR2 31:16 USB 310C E0CSR3 31:16 3110 USB E1CSR0 31:16 3114 USB E1CSR1 31:16 3118 USB E1CSR2 31:16 311C U
USB REGISTER MAP 1 (CONTINUED) 3128 USB E2CSR2 31:16 USB 312C E2CSR3 31:16 3130 USB E3CSR0 31:16 3134 USB E3CSR1 31:16 3138 USB E3CSR2 31:16 313C USB E3CSR3 31:16 3140 USB E4CSR0 31:16 3144 USB E4CSR1 31:16 3148 USB E4CSR2 31:16 USB 314C E4CSR3 31:16 3150 USB E5CSR0 31:16 3154 USB E5CSR1 31:16 3158 USB E5CSR2 31:16 USB 315C E5CSR3 31:16 3160 USB E6CSR0 31:16 3164 USB E6CSR1 31:16 3168 USB E6CSR2 31:16 316C USB E6CSR3 31:16 Legend: Note 1: 2: 3: 4: 15:0 15
USB REGISTER MAP 1 (CONTINUED) 3170 USB E7CSR0 31:16 3174 USB E7CSR1 31:16 3178 USB E7CSR2 31:16 USB 317C E7CSR3 31:16 3200 USB DMAINT 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF 3204 USB DMA1C 31:16 — — — — — — — — — — — — 15:0 — — — — — 3208 USB DMA1A 31:16 DMAADDR<31:16> 0000 15:0 DMAADDR<15:0> 0000 320C USB DMA1N 31:16 DMACOUNT<31:16> 0000 15:0 DMACOUNT<15:0> 32
USB REGISTER MAP 1 (CONTINUED) 3248 USB DMA5A 31:16 DMAADDR<31:16> 0000 15:0 DMAADDR<15:0> 0000 324C USB DMA5N 31:16 DMACOUNT<31:16> 0000 15:0 DMACOUNT<15:0> 3254 USB DMA6C 31:16 — — — — — 15:0 — — — — — 3258 USB DMA6A 31:16 DMAADDR<31:16> 0000 15:0 DMAADDR<15:0> 0000 325C USB DMA6N 31:16 DMACOUNT<31:16> 0000 15:0 DMACOUNT<15:0> 3264 USB DMA7C 31:16 — — — — — 15:0 — — — — — 3268 USB DMA7A 31:16 DMAADDR<31:16> 0000 15:0 DMAADDR<15:0> 0000 326
USB REGISTER MAP 1 (CONTINUED) Register Name Bit Range 3340 USB DPBFD 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — — — EP7TXD EP6TXD EP5TXD EP4TXD EP3TXD 15:0 — — — — — — — — EP7RXD EP6RXD EP5RXD EP4RXD EP3RXD 31:16 USB 3344 TMCON1 15:0 31:16 USB 3348 TMCON2 15:0 31:16 USB LPMR1 3364 USB LPMR2 20/4 19/3 18/2 17/1 16/0 EP2TXD EP1TXD — 0000 EP2RXD EP1RXD — 0000 05E6 TUCH<15:0> 4074 — — — — — — — — — — — — — — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 USBCSR0: USB CONTROL STATUS REGISTER 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS EP7TXIF EP6TXIF EP5TXIF EP4TXIF EP3TXIF EP2TXIF EP1TXIF EP0IF R/W-0 R/W-0 R/W-1 R-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-1: bit 10 USBCSR0: USB CONTROL STATUS REGISTER 0 (CONTINUED) RESUME: Resume from Suspend control bit 1 = Generate Resume signaling when the device is in Suspend mode 0 = Stop Resume signaling In Device mode, the software should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, the software should clear this bit after 20 ms.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 USBCSR1: USB CONTROL STATUS REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 USBCSR2: USB CONTROL STATUS REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 VBUSERRIE SESSRQIE DISCONIE R-0, HS R-0, HS Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 CONNIE SOFIE RESETIE RESUMEIE SUSPIE R-0, HS VBUSERRIF SESSRQIF DISCONIF R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS CONN
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-3: USBCSR2: USB CONTROL STATUS REGISTER 2 (CONTINUED) bit 19 SOFIF: Start of Frame Interrupt bit 1 = A new frame has started 0 = No start of frame detected bit 18 RESETIF: Reset/Babble Interrupt bit 1 = In Host mode, indicates babble is detected. In Device mode, indicates reset signaling is detected on the bus.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-4: Bit Range 31:24 23:16 15:8 7:0 USBCSR3: USB CONTROL STATUS REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FORCEHST FIFOACC FORCEFS FORCEHS PACKET TESTK TESTJ NAK U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — U-0 U-0 U-0 U-0 U-0 ENDPOINT<3:0> — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-4: USBCSR3: USB CONTROL STATUS REGISTER 3 (CONTINUED) bit 19-16 ENDPOINT<3:0>: Endpoint Registers Select bits 1111 = Reserved • • • 1000 = Reserved 0111 = Endpoint 7 • • • 0000 = Endpoint 0 These bits select which endpoint registers are accessed through addresses 3010-301F.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-5: Bit Range USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 0) Bit 31/23/15/7 U-0 31:24 23:16 15:8 7:0 Bit Bit 30/22/14/6 29/21/13/5 U-0 U-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0, HC R/W-0 R/W-0, HC — — — DISPING DTWREN DATATGGL R/W-0, HS R-0, HS R-0 — — — — R/W-0, HC R/W-0, HC R/W-0, HC R/C-0, HS SVCSETEND SVCRPR SENDSTAL
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-5: bit 21 USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 0) (CONTINUED) SENDSTALL: Send Stall Control bit (Device mode) 1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared. 0 = Do not send STALL handshake. REQPKT: IN transaction Request Control bit (Host mode) 1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-6: Bit Range 31:24 23:16 15:8 7:0 USBIE0CSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2 (ENDPOINT 0) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 U-0 U-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 U-0 U-0 U-0 — — — U-0 U-0 U-0 SPEED<1:0> U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — — U-0 U-0 U-0 NAKLIM<4:0> — — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-7: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 USBIE0CSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3 (ENDPOINT 0) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-1 R-0 R-x R-x R-0 R-x R-x MPRXEN MPTXEN BIGEND HBRXEN HBTXEN U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DYNFIFOS SOFTCONE UT
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-8: Bit Range 31:24 23:16 15:8 7:0 USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AUTOSET ISO — R/W-0, HS R/W-0, HC INCOMPTX NAKTMOUT CLRDT R/W-0 R/W-0 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-8: bit 23 USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) (CONTINUED) INCOMPTX: Incomplete TX Status bit (Device mode) 1 = For high-bandwidth Isochronous endpoint, a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts 0 = Normal operation In anything other than isochronous transfers, this bit will always return 0.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-8: USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) (CONTINUED) bit 15-11 MULT<4:0>: Multiplier Control bits For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1 for the payload size.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-9: USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) Bit Bit Range 31/23/15/7 R/W-0 31:24 15:8 7:0 Bit 29/21/13/5 R/W-0 R/W-0 ISO AUTOCLR AUTORQ R/W-0, HC 23:16 Bit 30/22/14/6 R/W-0, HS DMAREQEN R/W-0 SENTSTALL SENDSTALL CLRDT RXSTALL REQPKT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0, HC R-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-9: USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) (CONTINUED) bit 26 DATATWEN: Data Toggle Write Enable Control bit (Host mode) 1 = DATATGGL can be written 0 = DATATGGL is not writable bit 25 DATATGGL: Data Toggle bit (Host mode) When read, this bit indicates the current state of the endpoint data toggle. If DATATWEN = 1, this bit may be written with the required setting of the data toggle.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-9: bit 18 USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) (CONTINUED) OVERRUN: Data Overrun Status bit (Device mode) 1 = An OUT packet cannot be loaded into the RX FIFO. 0 = Written by software to clear this bit This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-10: USBIENCSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2 (ENDPOINT 1-7) Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 R/W-0 R/W-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 TXINTERV<7:0> R/W-0 R/W-0 SPEED<1:0> U-0 U-0 — — R-0 R-0 R/W-0 R/W-0 R/W-0 PROTOCOL<1:0>
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3 (ENDPOINT 1-7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x RXFIFOSZ<3:0> TXFIFOSZ<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3 (ENDPOINT 1-7) (CONTINUED) bit 15-8 RXINTERV<7:0>: Endpoint RX Polling Interval/NAK Limit bits For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-12: USBFIFOx: USB FIFO DATA REGISTER ‘x’ (‘x’ = 0-7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 DATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RXDPB U-0 U-0 U-0 R/W-0 — — — TXDPB U-0 U-0 U-0 U-0 RXFIFOSZ<3:0> R/W-0 R/W-0 TXFIFOSZ<3:0> U-0 U-0 R/W-0 R/W-0 RXEDMA — — — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED) bit 19-16 TXFIFOSZ<3:0>: TX Endpoint FIFO packet size bits The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission) 1111 = Reserved • • • 1010 = Reserved 1001 = 4096 bytes 1000 = 2048 bytes 0111 = 1024 bytes 0110 = 512 bytes 0101 = 256 bytes 0100 = 128 bytes 0011 = 64 bytes 0010 = 32 bytes 0001 = 16 by
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED) bit 0 SESSION: Active Session Control/Status bit ‘A’ device: 1 = Start a session 0 = End a session ‘B’ device: 1 = (Read) Session has started or is in progress, (Write) Initiate the Session Request Protocol 0 = When USB module is in Suspend mode, clearing this bit will cause a software disconnect Clearing this bit when the USB module is not suspended will result in undefine
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-14: USBFIFOA: USB FIFO ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFIFOAD<12:8> R/W-0 R/W-0 RXFIFOAD<7:0> U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-15: USBHWVER: USB HARDWARE VERSION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RC R-0 VERMAJOR<4:0> R-0 VERMINOR<9:8> R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-16: USBINFO: USB INFORMATION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 VPLEN<7:0> R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 WTCON<3:0> R-1 R-0 WTID<3:0> R-0 R-0 R-1 R-1 R-1 R-0 R-1 DMACHANS<3:0> R-0 R-1 R-0 RAMBITS<3:0> R-1
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-17: USBEOFRST: USB END-OF-FRAME/SOFT RESET CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — NRSTX NRST R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R.W-0 R/W-1 R/W-0 R.W-1 R/W-1 R/W-1 R.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-18: USBExTXA: USB ENDPOINT ‘x’ TRANSMIT ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — R/W-0 TXHUBPRT<6:0> R/W-0 R/W-0 R/W-0 MULTTRAN U-0 R/W-0 TXHUBADD<6:0> U-0 U-0 U-0 U-0 — — — — — — — — U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-19: USBExRXA: USB ENDPOINT ‘x’ RECEIVE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — R/W-0 RXHUBPRT<6:0> R/W-0 R/W-0 R/W-0 MULTTRAN U-0 R/W-0 RXHUBADD<6:0> U-0 U-0 U-0 U-0 — — — — — — — — U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-20: USBDMAINT: USB DMA INTERRUPT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0, HS R/W-0, HS R/W-0, HS R/W-0,
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-21: USBDMAxC: USB DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 1-8) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 DMABRSTM<1:0> — — — — — R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-22: USBDMAxA: USB DMA CHANNEL ‘x’ MEMORY ADDRESS REGISTER (‘x’ = 1-8) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 DMAADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAAD
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-24: USBExRPC: USB ENDPOINT ‘x’ REQUEST PACKET COUNT REGISTER (HOST MODE ONLY) (‘x’ = 1-7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-26: USBTMCON1: USB TIMING CONTROL REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 THHSRTN<15:8> R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 THHSRTN<7:0> R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 TUCH<15:8> R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 — — U-0 U-0 U-0 R/W-0 — — — LPMNAK R-0 R-0 R-0 R-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 LPMERRIE LPMRESIE LPMACKIE R/W-0 R-0 R-0 R-0 Legend: R = Readable bit -n = Value at POR Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 LPMSTIE LPMTOIE R/W-0 R/W-0, HC
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL REGISTER 1 (CONTINUED) bit 16 LPMXMT: LPM Transition to the L1 State bit When in Device mode: 1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must be set to ‘0b11. Both LPMXMT and LPMEN must be set in the same cycle.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0, HS R-0, HS
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2 bit 0 LPMSTIF: LPM STALL Interrupt Flag bit When in Device mode: 1 = A LPM transaction was received and the USB Module responded with a STALL 0 = No Stall condition When in Host mode: 1 = A LPM transaction was transmitted and the device responded with a STALL 0 = No Stall condition DS60001320B-page 246 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R/W-1, HS — — — — — USBIF USBRF USBWKUP U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — r-1 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER (CONTINUED) bit 3 SENDMONEN: Session End VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in Session End range (between 0.2V and 0.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.0 I/O PORTS Note: Some of the key features of the I/O ports are: • Individual output pin open-drain enable/disable • Individual input pin weak pull-up and pull-down • Monitor selective inputs and generate interrupt when change in pin state is detected • Operation during Sleep and Idle modes • Fast bit manipulation using CLR, SET and INV registers Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.1 12.1.3 Parallel I/O (PIO) Ports All port pins have up to 14 registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.2 Registers for Slew Rate Control Some I/O pins can be configured for various types of slew rate control on its associated port. This is controlled by the Slew Rate Control bits in the SRCON1x and SRCON0x registers that are associated with each I/O port. The slew rate control is configured using the corresponding bit in each register, as shown in Table 12-1.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.4.3 CONTROLLING PPS PPS features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-2: INPUT PIN SELECTION Peripheral Pin [pin name]R SFR [pin name]R bits INT3 INT3R INT3R<3:0> T2CK T2CKR T2CKR<3:0> T6CK T6CKR T6CKR<3:0> IC3 IC3R IC3R<3:0> IC7 IC7R IC7R<3:0> U1RX U1RXR U1RXR<3:0> U2CTS U2CTSR U2CTSR<3:0> U5RX U5RXR U5RXR<3:0> U6CTS U6CTSR U6CTSR<3:0> SDI1 SDI1R SDI1R<3:0> SDI3 SDI3R SDI3R<3:0> SDI5(1) SDI5R(1) SDI5R<3:0>(1) SS6(1) SS6R(1) SS6R<3:0>(1) REFCLKI1 REFCLKI1R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-2: INPUT PIN SELECTION (CONTINUED) Peripheral Pin [pin name]R SFR [pin name]R bits INT1 INT1R INT1R<3:0> T4CK T4CKR T4CKR<3:0> T9CK T9CKR T9CKR<3:0> IC1 IC1R IC1R<3:0> IC6 IC6R IC6R<3:0> U3CTS U3CTSR U3CTSR<3:0> U4RX U4RXR U4RXR<3:0> U6RX U6RXR U6RXR<3:0> SS2 SS2R SS2R<3:0> (1) Note 1: 2: 3: (1) SDI6 SDI6R SDI6R<3:0>(1) OCFA OCFAR OCFAR<3:0> REFCLKI3 REFCLKI3R REFCLKI3R<3:0> [pin name]R Va
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.4.5 OUTPUT MAPPING 12.4.6.1 In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 12-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-3: OUTPUT PIN SELECTION RPn Port Pin RPnR SFR RPnR bits RPD2 RPD2R RPD2R<3:0> RPG8 RPG8R RPG8R<3:0> RPF4 RPF4R RPF4R<3:0> RPD10 RPD10R RPD10R<3:0> RPF1 RPF1R RPF1R<3:0> RPB9 RPB9R RPB9R<3:0> RPB10 RPB10R RPB10R<3:0> RPC14 RPC14R RPC14R<3:0> RPB5 RPB5R RPB5R<3:0> RPC1(1) RPC1R(1) RPC1R<3:0>(1) RPD14(1) RPD14R(1) RPD14R<3:0>(1) RPG1(1) RPG1R(1) RPG1R<3:0>(1) RPA14(1) RPA14R(1) RPA14R<3:0>(1)
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-3: OUTPUT PIN SELECTION (CONTINUED) RPn Port Pin RPnR SFR RPnR bits RPD1 RPD1R RPD1R<3:0> RPG9 RPG9R RPG9R<3:0> RPB14 RPB14R RPB14R<3:0> RPD0 RPD0R RPD0R<3:0> RPB6 RPB6R RPB6R<3:0> RPD5 RPD5R RPD5R<3:0> RPB2 RPB2R RPB2R<3:0> RPF3 RPF3R RPF3R<3:0> (1) RPF13R RPF13R<3:0>(1) RPC2(1) RPC2R(1) RPC2R<3:0>(1) RPE8(1) RPE8R(1) RPE8R<3:0>(1) RPF2(1) RPF2R(1) RPF2R<3:0>(1) RPF13 Note 1: 2: 3: (1) RP
I/O Ports Control Registers ANSELA 0010 0020 0030 Preliminary 0040 TRISA PORTA LATA ODCA 0050 CNPUA 0060 CNPDA 0070 CNCONA 0080 CNENA 0090 CNSTATA 2015 Microchip Technology Inc.
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF86_#) PORTB REGISTER MAP Preliminary 0100 ANSELB 31:16 15:0 — ANSB15 — ANSB14 — ANSB13 — ANSB12 — ANSB11 — ANSB10 — ANSB9 — ANSB8 — ANSB7 — ANSB6 — ANSB5 — ANSB41 — ANSB3 — ANSB2 — ANSB1 — ANSB0 0000 FFFF 0110 TRISB 31:16 — 15:0 TRISB15 — TRISB14 — TRISB13 — TRISB12 — TRISB11 — TRISB10 — TRISB9 — TRISB8 — TRISB7
TRISC 0220 PORTC 0230 LATC 0240 ODCC 0250 CNPUC 0260 CNPDC 0270 CNCONC CNENC 17/1 16/0 All Resets Preliminary 0210 Bit Range Register Name(1) Virtual Address (BF86_#) Bits 0200 ANSELC 0280 PORTC REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY — — — 0000 ANSC2 — ANSC1 — — — 001E 0000 TRISC2 — TRISC1 — — — F01E 0000 RC3 — RC2 — RC1 — — — xxxx 0000 LATC4 — LATC3 — LATC2 — LATC1 — — — xxxx 0000 — — ODCC4 — ODCC3 — ODCC2 — ODCC1 — — — 0000 0000 —
Virtual Address (BF86_#) Register Name(1) 0210 TRISC 0220 PORTC 0230 LATC 0240 ODCC 0250 CNPUC 0260 CNPDC Preliminary CNENC 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 0270 CNCONC 0280 PORTC REGISTER MAP FOR 64-PIN DEVICES ONLY 31:16 — — — — — — — — — — — — — — — — 0000 15:0 31:16 TRISC15 — TRISC14 — TRISC13 — TRISC12 — — — — — — — — — — — — — — — — — — — — — — — — — F
Preliminary 0310 TRISD 0320 PORTD 0330 LATD 0340 ODCD 0350 CNPUD 0360 CNPDD 0370 CNCOND CNEND 0390 CNSTATD 03A0 CNNED 03B0 CNFD 2015 Microchip Technology Inc.
Preliminary 0310 TRISD 0320 PORTD 0330 LATD 0340 ODCD 0350 CNPUD 0360 CNPDD 0370 CNCOND CNEND 0390 CNSTATD 31:16 31/15 — 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits 0300 ANSELD 0380 PORTD REGISTER MAP FOR 100-PIN DEVICES ONLY — — — — — — — — — — — — — — — 0000 15:0 ANSD15 31:16 — ANSD14 — — — — — — — — — — — — — — — — — — — — — — — — —
Virtual Address (BF86_#) Register Name(1) 0310 TRISD 0320 PORTD 0330 LATD 0340 ODCD 0350 CNPUD 0360 CNPDD Preliminary 0370 CNCOND 0380 CNEND 0390 CNSTATD 03A0 CNNED 03B0 CNFD Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 31:16 — — — — — 15:0 31:16 — — — — — — — — TRISD11 — 15:0 31:16 — — — — — — — — RD11 — 15:0 31:16 — — — — — — — — 15:0 31:16 — — — — — — — — 15:0 31:16 — — — — — — — — 15:0 31:16 — — — — — — — — 15:0 ON — SIDL — 31:16 1
Virtual Address (BF86_#) Register Name(1) ANSELE 0410 TRISE 0420 PORTE 0430 LATE 0440 ODCE 0450 CNPUE 0460 CNPDE 0470 CNCONE 0480 CNENE 0490 CNSTATE Bit Range 20/4 19/3 18/2 17/1 16/0 All Resets Preliminary 0400 Bits — — — — — — 0000 ANSE5 — ANSE4 — — — — — — — — — 03F0 0000 TRISE5 — TRISE4 — TRISE3 — TRISE2 — TRISE1 — TRISE0 — 03FF 0000 RE6 — RE5 — RE4 — RE3 — RE2 — RE1 — RE0 — xxxx 0000 LATE7 — LATE6 — LATE5 — LATE4 — LATE3 — LATE2 — LATE1 —
Virtual Address (BF86_#) Preliminary 0410 TRISE 0420 PORTE 0430 LATE 0440 ODCE 0450 CNPUE 0460 CNPDE 0470 CNCONE 0480 CNENE 0490 CNSTATE 04A0 CNNEE 04B0 CNFE 2015 Microchip Technology Inc.
Preliminary 0510 TRISF 0520 PORTF 0530 LATF 0540 ODCF 0550 CNPUF 0560 CNPDF 0570 CNCONF 0580 CNENF 0590 CNSTATF 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 0500 ANSELF Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — — — — — — — — — — — — — 0000 ANSF13 — ANSF12 — — — — — — — — — — — — — — — — — — — — — — — — — 3000 0000 TRISF13 — TRISF12 — — — — — — — TRISF8 — — — — — TRISF5 — TRISF4 —
Virtual Address (BF86_#) Register Name(1) 0510 TRISF 0520 PORTF 0530 LATF 0540 ODCF 0550 CNPUF 0560 CNPDF 0580 CNENF 0590 CNSTATF 16/0 All Resets Preliminary 0570 CNCONF Bit Range Bits — — 0000 TRISF1 — TRISF0 — 003B 0000 RF1 — RF0 — xxxx 0000 — — LATF1 — LATF0 — xxxx 0000 ODCF3 — — — ODCF1 — ODCF0 — 0000 0000 CNPUF4 — CNPUF3 — — — CNPUF1 — CNPUF0 0000 — 0000 CNPDF5 — CNPDF4 — CNPDF3 — — — CNPDF1 — CNPDF0 0000 — 0000 — — — — — — — — — — — CNENF5 —
Preliminary 0610 TRISG 0620 PORTG 0630 LATG 0640 ODCG 0650 CNPUG 0660 CNPDG 0670 CNCONG 0680 CNENG 0690 CNSTATG 06A0 CNNEG 06B0 CNFG 06C0 SRCON0G 06D0 SRCON1G DS60001320B-page 269 Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — — — — — — — — 15:0 31:16 ANSG15 — — — — — — — — — — — ANSG9 — ANSG8 — — — — — TRISG9 — TRISG8 — 15:0 TRISG15 31:16 — TRISG14 TRISG13 TRISG12 — — — 25/9 24/8 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 0600
Preliminary 0610 TRISG 0620 PORTG 0630 LATG 0640 ODCG 0650 CNPUG 0660 CNPDG 0670 CNCONG 0680 CNENG 0690 CNSTATG 06A0 06B0 CNNEG CNFG 2015 Microchip Technology Inc.
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits Preliminary 0700 ANSELH 31:16 15:0 — — — — — — — — — — — — — — — — — — — ANSH6 — ANSH5 — ANSH4 — — — — — ANSH1 — 0000 ANSH0 0073 0710 TRISH 31:16 15:0 — — — — — TRISH13 — TRISH12 — — — TRISH10 — TRISH9 — TRISH8 — — — TRISH6 — TRISH5 — TRISH4 — — — — — TRISH1 — 0000 TRISH0 3773 0720 PORTH 31:16 15
16/0 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 — — — — — — — — — — — — — — — — — — — ANSH6 — ANSH5 — ANSH4 — — — — — ANSH1 — 0000 ANSH0 0073 — TRISH14 — TRISH13 — TRISH12 — TRISH11 — TRISH10 — TRISH9 — TRISH8 — TRISH7 — TRISH6 — TRISH5 — TRISH4 — TRISH3 — TRISH2 — TRISH1 — 0000 TRISH0 FFFF Preliminary 0700 ANSELH 31:16 15:0 0710 TRISH 31:16 — 15:
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — 0000 0B00 Preliminary 0800 ANSELJ 31:16 15:0 — — — — — — — — — ANSJ11 — — — ANSJ9 — ANSJ8 — — — — — — — — — — — — — — 0810 TRISJ 31:16 15:0 — — — — — — — — — TRISJ11 — — — TRISJ9 — TRISJ8 — — — — — — — TRISJ4 — — — TRISJ2 — TRISJ1 0820 PORTJ 31:16 15:0 — — — — — — — — — RJ11 — — — RJ9
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — — — — — — — — ANSJ11 — — — ANSJ9 — ANSJ8 — — — — — — — — — — — — — — — — 0000 0B00 — TRISJ14 — TRISJ13 — TRISJ12 — TRISJ11 — TRISJ10 — TRISJ9 — TRISJ8 — TRISJ7 — TRISJ6 — TRISJ5 — TRISJ4 — TRISJ3 — TRISJ2 — TRISJ1 Preliminary 0800 ANSELJ 31:16 15:0 0810 TRISJ 31:16 — 15:0 TRISJ15 0820 PORTJ 31
Virtual Address (BF86_#) Register Name(1) Bit Range Preliminary 0910 TRISK 31:16 15:0 — — — — — — — — — — — — — — — — — TRISK7 — TRISK6 — TRISK5 — TRISK4 — TRISK3 — TRISK2 — TRISK1 0920 PORTK 31:16 15:0 — — — — — — — — — — — — — — — — — RK7 — RK6 — RK5 — RK4 — RK3 — RK2 — RK1 — RK0 0000 xxxx 0930 LATK 31:16 15:0 — — — — — — — — — — — — — — — — — LATK7 — LATK6 — LATK5 — LATK4 — LATK3 — LATK2 — LATK1 — LATK0 0000 xxxx 0940 ODCK 31:16 15:0 — — —
2015 Microchip Technology Inc.
DS60001320B-page 277 IC4R 1448 IC5R 144C IC6R 1450 IC7R 1454 IC8R 1458 IC9R 1460 OCFAR 1468 U1RXR 146C U1CTSR 1470 U2RXR 1474 U2CTSR 1478 U3RXR 147C U3CTSR 1480 U4RXR 1484 U4CTSR Legend: Note 1: 2: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — —
2015 Microchip Technology Inc.
SS6R(1) 14E0 C1RXR(2) 14E4 C2RXR(2) 14E8 REFCLKI1R 14F0 REFCLKI3R 14F4 REFCLKI4R Legend: Note 1: 2: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — —
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Preliminary 2015 Microchip Technology Inc.
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Preliminary DS60001320B-page 281 — — — — — — — — 31:16 15:0 — — — — — — — — — — — — — — — — 31:16 15B8 RPC14R 15:0 — — — — — — — — 31:16 — — — — — — — — 15C0 RPD0R — — — — — — — — 15:0 31:16 — — — — — — — — 15C4 RPD1R 15:0 — — — — — — — — — — — — — — — — 31:16 15C8 RPD2R 15:0 — — — — — — — — 31:16 — — — — — — — — 15CC RPD3R — — — — — — — — 15:0 31:16 — — — — — — — — 15D0 RPD4R 15:0 — — — — — — — — — — — — — — — — 31:16 15D4 RPD5R 15:0 — — — — — — — — 31
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 12-3: Bit Range 31:24 23:16 15:8 7:0 CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A – K) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — R/W-0 U-0 — R/W-0 U-0 R/W-0 U-0 U-0 U-0 ON — SIDL — EDGEDETECT — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 13.0 Note: TIMER1 The following modes are supported by Timer1: • • • • This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS60001105) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 13.
Timer1 Control Register Virtual Address (BF84_#) TABLE 13-1: TMR1 0020 Legend: Note 1: PR1 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — 15:0 31:16 ON — — — SIDL — 15:0 31:16 — — — — 23/7 22/6 21/5 20/4 19/3 — — — — TWDIS — TWIP — — — — — — — — TMR1<15:0> — — — — — — — — — — TGATE — — — TCKPS<1:0> — — — — — — — — 15:0 PR1<15:0> x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 ON — SIDL TWDIS TWIP — — — R/W-0 U-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 14.0 Note: TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 Four 32-bit synchronous timers are available by combining Timer2 with Timer3, Timer4 with Timer5, Timer6 with Timer7, and Timer8 with Timer9. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 14-2: TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 BLOCK DIAGRAM (32-BIT) Reset TMRy(2) MS Half Word ADC Event Trigger(1) TMRx(2) LS Half Word 32-bit Comparator Equal PRy(2) TyIF Event Flag(2) Sync PRx(2) 0 1 Q D TGATE Q TCS TGATE ON TxCK(2) x1 Gate Sync PBCLK3 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1: 2: ADC event trigger is available only on the Timer2/3 and TImer4/5 pairs.
Timer2-Timer9 Control Registers Virtual Address (BF84_#) TABLE 14-1: TIMER2 THROUGH TIMER9 REGISTER MAP All Resets Bit Range Register Name(1) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — TGATE — — TCKPS<2:0> — — T32 — — — TCS — — 0000 0000 Preliminary DS60001320B-page 291 0200 T2CON 31:16 15:0 — ON — — — SIDL — — — — — — — — — — 0210 TMR2 31:16 15:0 — — — — — — — — — TMR2<15:0> — — — — — — — 0000 000
Virtual Address (BF84_#) 0C20 PR7 0E00 T8CON 0E10 TMR8 0E20 PR8 1000 T9CON Preliminary TMR9 1020 PR9 31:16 All Resets Bit Range Register Name(1) Bits 0C10 TMR7 1010 TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 0000 15:0 31:16 — — — — — — — TMR7<15:0> — — 15:0 31:16 — — — — — — — PR7<15:0> — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 14-1: Bit Range 31:24 23:16 15:8 7:0 TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(1) — SIDL(2) — — — — — R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 14-1: TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9) (CONTINUED) bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(1) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5, Timer7, and Timer9).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 15.0 DEADMAN TIMER (DMT) Note: The DMT consists of a 32-bit counter with a time-out count match value as specified by the DMTCNT<3:0> bits in the DEVCFG1 Configuration register. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9.
Deadman Timer Control Registers Virtual Address (BF80_#) Register Name TABLE 15-1: 0A00 DMTCON DEADMAN TIMER REGISTER MAP 0A10 DMTPRECLR 0A20 DMTCLR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — — — — — — — — — — — — — x000 31:16 — — — — — — — — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — — — 0000 — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-1: Bit Range DMTCON: DEADMAN TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-y (1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-3: Bit Range Bit 30/22/14/6 U-0 U-0 31:24 23:16 15:8 7:0 DMTCLR: DEADMAN TIMER CLEAR REGISTER Bit 31/23/15/7 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STEP2<7:0> Legend: R = Readable bit -n = Value a
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-4: Bit Range Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 31:24 23:16 15:8 7:0 DMTSTAT: DEADMAN TIMER STATUS REGISTER Bit 31/23/15/7 bit 6 bit 5 bit 4-1 bit 0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HC, HS R-0, HC, HS R-0, HC, HS U-0 U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-5: Bit Range DMTCNT: DEADMAN TIMER COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 COUNTER<15:8> 7:0 R-0 R-0 COUNTER<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown COU
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-7: Bit Range DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 R-0 R-0 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-y R-y R-y PSINTV<31:24> 23:16 R-0 R-0 PSINTV<23:16> 15:8 R-0 R-0 PSINTV<15:8> 7:0 R-0 R-0 PSINTV<7:0> Legend: R = Readable bit -n = Value at POR bit 31-8
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 302 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 16.0 Note: WATCHDOG TIMER (WDT) When enabled, the Watchdog Timer (WDT) operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode.
Watchdog Timer Control Registers 0800 WDTCON(1) Legend: Note 1: WATCHDOG TIMER REGISTER MAP 31/15 30/14 29/13 ON — — 28/12 27/11 26/10 31:16 15:0 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 — — — — — WDTCLRKEY<15:0> RUNDIV<4:0> — — 16/0 All Resets Bit Range Bits Register Name Virtual Address (BF80_#) TABLE 16-1: 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 16-1: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 W-0 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 W-0 W-0 Bit Bit 27/19/11/3 26/18/10/2 W-0 W-0 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 R-y R-y R-y WDTCLRKEY<15:8> W-0 W-0 W-0 W-0 W-0 R/W-y (1) U-0 U-0 — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — WDTWINEN WDTCLRKEY<7:0> ON R-y R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 306 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 17.0 INPUT CAPTURE Note: • Prescaler capture event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The timer source for each Input Capture module depends on the setting of the ICACLK bit in the CFGCON register. The available configurations are shown in Table 17-1.
Input Capture Control Registers INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP 2000 IC1CON(1) 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — Preliminary DS60001320B-page 309 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 31:16 2010 IC1BUF IC1BUF<31:0> 15:0 31:16 — — — — — — — — — — — — — — — — 2200 IC2CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE X CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 Note 1: Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 18.0 OUTPUT COMPARE Note: When a match occurs, the Output Compare module generates an event based on the selected mode of operation. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The timer source for each Output Compare module depends on the setting of the OCACLK bit in the CFGCON register. The available configurations are shown in Table 18-1.
Output Compare Control Registers Virtual Address (BF84_#) TABLE 18-2: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — ON — — — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM<2:0> — All Resets Bit Range Register Name(1) Bits 4000 OC1CON 31:16 15:0 4010 OC1R 31:16 15:0 OC1R<31:0> xxxx xxxx 4020 OC1RS 31:16 15:0 OC1RS<31:0> xxxx xxxx — ON Prelimin
Virtual Address (BF84_#) 4A10 OC6R OC6RS 4C00 OC7CON 4C10 OC7R 4C20 OC7RS Preliminary 4E00 OC8CON 4E10 OC8R 4E20 OC8RS 5000 OC9CON 5010 5020 OC9R 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — 15:0 ON — — — — — — — — — — — SIDL — — — — — — — OC32 31:16 21/5 20/4 19/3 18/2 — — — OCFLT OCTSEL 31:16 — 0000 xxxx xxxx xxxx — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL 31:16 15:0 — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON — SIDL — — — — — U-0 U-0 R/W-0 R-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 316 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The SPI/I2S module is compatible with Motorola® SPI and SIOP interfaces. 19.
SPI Control Registers SPI1 THROUGH SPI6 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 1000 SPI1CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> 15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE 1010 SPI1STAT 31:16 15:0 1020 SPI1BUF 31:16 15:0 1030 SPI1BRG 31:16 15:0 — — Preliminary 1200 SPI2CON 1210 SPI2STAT 1220 SPI2BUF 1230 SPI2BRG 1240 SPI2CON2 1400 SPI3CON 2015 Microchip Technology Inc.
1600 SPI4CON 1610 SPI4STAT 1620 SPI4BUF 1630 SPI4BRG 1640 SPI4CON2 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 31:16 ON — — — SIDL — DISSDO MODE32 MODE16 SMP RXBUFELM<4:0> 15:0 31:16 — — — FRMERR SPIBUSY 24/8 FRMCNT<2:0> — — 17/1 — — SPIFE — — MSTEN — DISSDI SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF 16/0 ENHBUF 0000 STXISEL<1:0> SRXISEL<1:0> TXBUFELM<4:0> DATA<31:0> 0000 0000 SPIRBF 0008 0000 Preliminary 15:0 31:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 FRMCNT<2:0> R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 MCLKSEL(1) — — — — — SPIFE ENHBUF(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(1) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI/I2S Module On bit 1 = SPI/I2S module is enabled 0 = SP
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-1: bit 5 SPIxCON: SPI CONTROL REGISTER (CONTINUED) MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode DISSDI: Disable SDI bit(4) 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is ge
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPI CONTROL REGISTER 2 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPISGNEXT — — FRMERREN SPIROVEN R/W-0 U-0 U-0 U-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — U-0 U-0 U-0 R-0 R-0 — — — U-0 U-0 U-0 R/C-0, HS R-0 U-0 R-0 SPITUR RXBUFELM<4:0> R-0 R-0 R-0 TXBUFELM<4:0> U-0 — — — FRMERR SPIBUSY — — R-0 R/W-0 R-0 U-0 R-1 U
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-3: SPIxSTAT: SPI STATUS REGISTER bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 326 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 20.0 Note: SERIAL QUAD INTERFACE (SQI) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 46. “Serial Quad Interface (SQI)” (DS60001244) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
SQI Control Registers Register Name Bit Range SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP Virtual Address (BF8E_#) TABLE 20-1: 2000 SQI1 XCON1 31:16 SQI1 XCON2 31:16 — — — — — 15:0 — — — — DEVSEL<1:0> 31:16 — — — — — — 15:0 — — — BURSTEN — HOLD WP 31:16 — — — — — — — 2004 2008 SQI1CFG 200C SQI1CON 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — DDRDATA DDR DUMMY DDR MODE DDR ADDR DDRCMD 15:0 READOPCODE<5:0> Preliminary 2010 2014 31:1
Virtual Address (BF8E_#) Register Name Bit Range SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP (CONTINUED) 2044 SQI1BD STAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 — — — — — — — — — — 15:0 — SQI1BD 31:16 204C TXDSTAT 15:0 — — — — — — SQI1BD 31:16 2050 RXDSTAT 15:0 — — — — — — — — — — — 31:16 — — — — — — — — — 15:0 — — — — — — — — — 31:16 — — — — — — — — — 15:0 — — — — DMAEISE 31:16 — — — — 15:0 —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-1: Bit Range SQI1XCON1: SQI XIP CONTROL REGISTER 1 Bit Bit 31/23/15/7 30/22/14/6 31:24 23:16 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 R/W-0 — — — DDRDATA R/W-0 R/W-0 R/W-0 R/W-0 DUMMYBYTES<2:0> R/W-0 15:8 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 R/W-0 R/W-0 R/W-0 DDRDUMMY DDRMODE DDRADDR R/W-0 R/W-0 ADDRBYTES<2:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TYPEDUMMY<1:0> R/W-0 DDRCMD R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-1: SQI1XCON1: SQI XIP CONTROL REGISTER 1 (CONTINUED) bit 17-10 READOPCODE<7:0>: Op code Value for Read Operation bits These bits contain the 8-bit op code value for read operation. bit 9-8 TYPEDATA<1:0>: SQI Type Data Enable bits The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-2: Bit Range 31:24 23:16 15:8 7:0 SQI1XCON2: SQI XIP CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 DEVSEL<1:0> R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-3: Bit Range 31:24 23:16 15:8 7:0 SQI1CFG: SQI CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — R/W-0 U-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC CON FIFORST RX FIFORST TX FIFORST RESET U-0 SQIEN — DATAEN<1:0> CSEN<1:0> U-0 r-0 r-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-3: SQI1CFG: SQI CONFIGURATION REGISTER (CONTINUED) bit 12 BURSTEN: Burst Configuration bit(1) 1 = Burst is enabled 0 = Burst is not enabled bit 11 Reserved: Must be programmed as ‘0’ bit 10 HOLD: Hold bit In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is connected.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 SQI1CON: SQI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 U-0 U-0 r-0 R/W-0 — — — — — — — SCHECK R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DDRMODE DASSERT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DEVSEL<1:0> LANEMODE<1:0> R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 CMDINIT<1:0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 SQI1CLKCON: SQI CLOCK CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) R/W-0 U-0 U-0 U-0 U-0 U-0 — — — — — CLKDIV<9:8>(1) R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-6: Bit Range 31:24 23:16 15:8 7:0 SQI1CMDTHR: SQI COMMAND THRESHOLD REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 U-0 U-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-7: Bit Range 31:24 23:16 15:8 7:0 SQI1INTTHR: SQI INTERRUPT THRESHOLD REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-8: Bit Range 31:24 23:16 15:8 7:0 SQI1INTEN: SQI INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — DMAEIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-9: Bit Range 31:24 23:16 15:8 7:0 SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — — — — DMA EIF PKT COMPIF
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-9: SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED) bit 2 TXTHRIF: Transmit Buffer Threshold Interrupt Flag bit 1 = Transmit buffer has more than TXINTTHR words of space available 0 = Transmit buffer has less than TXINTTHR words of space available bit 1 TXFULLIF: Transmit Buffer Full Interrupt Flag bit 1 = The transmit buffer is full 0 = The transmit buffer is not full bit 0 TXEMPTYIF: Transmit Buffer Empty Interrupt
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-10: SQI1TXDATA: SQI TRANSMIT DATA BUFFER REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-12: SQI1STAT1: SQI STATUS REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TXFIFOFREE<7:0> RXFIFOCNT<7:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-13: SQI1STAT2: SQI STATUS REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 — — — — — — CMDSTAT<1:0> U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — R-0 R-0 R-0 R-0 R-0 U-0 R-0 R-0 CONAVAIL<0>
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-14: SQI1BDCON: SQI BUFFER DESCRIPTOR CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-16: SQI1BDBASEADD: SQI BUFFER DESCRIPTOR BASE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDADDR<31:24> R/W-0 BDADDR<23
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-18: SQI1BDPOLLCON: SQI BUFFER DESCRIPTOR POLL CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-20: SQI1BDRXDSTAT: SQI BUFFER DESCRIPTOR DMA RECEIVE STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-x R-x R-x R-x U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 RXSTATE<3:0> R-x R-x — R-x R-x R-x U-0 U-0 RXBUFCNT<4:0> U-0 U-0 U-0 — — — — — — — — R-x R-x R-x
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-22: SQI1INTSIGEN: SQI INTERRUPT SIGNAL ENABLE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — DMAEISE PKT DONEISE BD DONEI
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-23: SQI1TAPCON: SQI TAP CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-24: SQI1MEMSTAT: SQI MEMORY STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — STATPOS R/W-0 R/W-0 R/W-0 R/W-0 STATTYPE<1:0> R/W-0 STATBYTES<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-25: SQI1XCON3: SQI XIP CONTROL REGISTER 3 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 R/W-0 — — — INIT1SCHECK R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit Bit 27/19/11/3 26/18/10/2 R/W-0 R/W-0 INIT1COUNT<1:0> Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 INIT1TYPE<1:0> R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-26: SQI1XCON4: SQI XIP CONTROL REGISTER 4 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 R/W-0 — — — INIT2SCHECK R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit Bit 27/19/11/3 26/18/10/2 R/W-0 R/W-0 INIT2COUNT<1:0> Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 INIT2TYPE<1:0> R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 354 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 21.0 Note: Each I2C module offers the following key features: INTER-INTEGRATED CIRCUIT™ (I2C™) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit™ (I2C™)” (DS60001116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 21-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read PBCLK2
I2C Control Registers Register Name(1) Preliminary Virtual Address (BF82_#) TABLE 21-1: 0000 I2C1CON 0010 I2C1STAT 0020 I2C1ADD 0030 I2C1MSK 0040 I2C1BRG 0050 I2C1TRN 0060 I2C1RCV I2C1 THROUGH I2C5 REGISTER MAP 0200 I2C2CON(2) 0210 I2C2STAT(2) 0220 I2C2ADD(2) 0230 I2C2MSK(2) 0240 I2C2BRG(2) 0250 I2C2TRN(2) 0260 I2C2RCV(2) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — — 15:0 ON — 31:16 — — 15:0 ACKSTAT TRSTAT 31:16 — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — 15:
0440 0450 0460 0600 0610 Preliminary 0620 0630 0640 0650 0660 31/15 30/14 31:16 — — 15:0 — — 31:16 — — I2C3BRG 15:0 31:16 — — I2C3TRN 15:0 — — 31:16 — — I2C3RCV 15:0 — — 31:16 — — I2C4CON 15:0 ON — 31:16 — — I2C4STAT 15:0 ACKSTAT TRSTAT 31:16 — — I2C4ADD 15:0 — — 31:16 — — I2C4MSK 15:0 — — 31:16 — — I2C4BRG 15:0 31:16 — — I2C4TRN 15:0 — — 31:16 — — I2C4RCV 15:0 — — I2C3MSK 28/12 27/11 26/10 25/9 24/8 23/7 22/6 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — S
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2C CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 ON — SIDL SCKRE
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-1: bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 I2CXCON: I2C CONTROL REGISTER (CONTINUED) SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HS, HC R-0, HS, HC R/C-0, HS, HC U-0 U-0 R/C-0, HS R-0, HS, HC R-0, HS, HC ACKSTAT TRSTAT ACKTIM
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED) bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 22.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.
UART Control Registers Virtual Address (BF82_#) TABLE 22-1: U1STA(1) 2020 U1TXREG 2030 U1RXREG Preliminary 2040 U1BRG(1) 2200 U2MODE(1) 2210 U2STA(1) 2220 U2TXREG 2230 U2RXREG 2240 (1) U2BRG 2400 U3MODE(1) 2410 U3STA(1) 2015 Microchip Technology Inc.
Virtual Address (BF82_#) U4STA(1) 2620 U4TXREG 2630 U4RXREG 2640 U4BRG(1) 2800 U5MODE(1) Preliminary 2810 U5STA (1) 2830 U5RXREG 2840 U5BRG(1) 2A00 U6MODE(1) 2A10 U6STA(1) 2A20 U6TXREG 2A30 U6RXREG DS60001320B-page 365 (1) 2A40 U6BRG 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — 31:16 15:0 — — — — — — ON — SIDL IREN RTSMD — 31:16 — — — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 15:0 UTXISEL<1:0> UEN<1:0> 31:16 — — — — — — — — 15:0 —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 (1) ON — SIDL IREN RTSMD — R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x ba
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Figure 22-2 and Figure 22-3 illustrate typical receive and transmit timing for the UART module.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 23.0 PARALLEL MASTER PORT (PMP) Note: Key features of the PMP module include: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS60001128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PMP Control Registers Register Name(1) Bit Range PARALLEL MASTER PORT REGISTER MAP Virtual Address (BF82_#) TABLE 23-1: E000 PMCON 31:16 15:0 — ON E010 PMMODE 31:16 15:0 — BUSY 31:16 E020 PMADDR — CS2 — CS1 31:16 ADDR15 — 15:0 31:16 15:0 31:16 E030 PMDOUT E040 Preliminary E050 E060 PMDIN PMAEN PMSTAT E070 PMWADDR E090 Legend: 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 PMCON: PARALLEL PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0, HC U-0 U-0 U-0 U-0 U-0 R/W-0 RDSTART — — — — — DUALBUF — R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON — SIDL PMPTTL PTWREN PT
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 7-6 CSF<1:0>: Chip Select Function bits(1) 11 = Reserved 10 = PMCS1 and PMCS2 function as Chip Select 01 = PMCS2 functions as Chip Select and PMCS1 functions as address bit 14 00 = PMCS1 and PMCS2 function as address bit 14 and address bit 15 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip S
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 (1) INCM<1:0> R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPBCLK2 • • • 0001 = Wait of 2 TPBCLK2 0000 = Wait of 1 TPBCLK2 (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPBCLK2 10 = Wait of 3 TPBCLK2 01 = Wait of 2 TPBCLK2 00 = Wait of 1 TPBCLK2 (default) For Read operations: 11 = Wait of 3 TPBCLK2 10
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-3: Bit Range 31:24 23:16 15:8 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) R/W-0 (3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 CS1 ADDR15(2) ADD
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-4: Bit Range 31:24 23:16 15:8 7:0 PMDOUT: PARALLEL PORT OUTPUT DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 D
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-6: Bit Range 31:24 23:16 15:8 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<15:14> R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-7: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0, HS, SC U-0 U-0 R-0 R-0 R-0 R-0 IB0F IBF IBOV — — IB3F IB2F
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-8: Bit Range 31:24 23:16 15:8 7:0 PMWADDR: PARALLEL PORT WRITE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) WCS2 R/W-0 (3) WCS1 WADDR
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-9: Bit Range 31:24 23:16 15:8 7:0 PMRADDR: PARALLEL PORT READ ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) RCS2 R/W-0 (3) RCS1 RADDR1
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-10: PMRDIN: PARALLEL PORT READ INPUT DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 384 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 24.0 EXTERNAL BUS INTERFACE (EBI) Note: TABLE 24-1: Feature This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 47. “External Bus Interface (EBI)” in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/ PIC32).
EBI Control Registers Virtual Address (BF8E_#) Register Name TABLE 24-2: 1014 EBICS0 EBI REGISTER MAP 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — — — 31:16 15:0 EBICS1(1) 31:16 101C EBICS2(1) 31:16 1018 31/15 15:0 15:0 23/7 — — — — — — — — — — — — — Preliminary 31:16 15:0 — — — — — — — — — — — — — REGSEL<2:0> — 1058 EBIMSK1(1) 31:16 — — — — — — — — 15:0 — — — — — 105C EBIMSK2(1) 31:16 — — — — — 15:0 — — — — — EBIMSK3(
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 EBICSx: EXTERNAL BUS INTERFACE CHIP SELECT REGISTER (‘x’ = 0-3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CSADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSADDR<7:0> U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-2: Bit Range 31:24 23:16 15:8 7:0 EBIMSKx: EXTERNAL BUS INTERFACE ADDRESS MASK REGISTER (‘x’ = 0-3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-3: Bit Range 31:24 23:16 15:8 7:0 EBISMTx: EXTERNAL BUS INTERFACE STATIC MEMORY TIMING REGISTER (‘x’ = 0-2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-1 R/W-0 R/W-0 — RDYMODE R/W-1 R/W-1 R/W-1 TPRC<3:0>(1) PAGEMODE R/W-0 Bit 26/18/10/2 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-4: Bit Range 31:24 23:16 15:8 7:0 EBIFTRPD: EXTERNAL BUS INTERFACE FLASH TIMING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-5: Bit Range Bit 31/23/15/7 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 23:16 7:0 Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 31:24 15:8 EBISMCON: EXTERNAL BUS INTERFACE STATIC MEMORY CONTROL REGISTER SMDWIDTH2<2:0> SMDWID
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 392 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 25.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) Key features of the RTCC module include: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.
RTCC Control Registers RTCC REGISTER MAP 31/15 30/14 29/13 28/12 27/11 — ON — — — SIDL — — — — — CHIME — PIV — ALRMSYNC — Preliminary 0C00 RTCCON 31:16 15:0 0C10 RTCALRM 31:16 — 15:0 ALRMEN 0C20 RTCTIME 31:16 15:0 HR10<3:0> SEC10<3:0> 0C30 RTCDATE 31:16 15:0 0C40 ALRMTIME 31:16 15:0 0C50 ALRMDATE 31:16 15:0 Legend: Note 1: — 26/10 25/9 24/8 23/7 22/6 — RTCCLKSEL<1:0> RTCOUTSEL<1:0> RTCCLKON CAL<9:0> — — — HR01<3:0> SEC01<3:0> — MIN10<3:0> — — — YEAR10<3:0> DAY10<3:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-1: Bit Range Bit 31/23/15/7 23:16 Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 CAL<9:8> CAL<7:0> 15:8 7:0 RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 ON(1) — SIDL — — RTCCLK
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-1: RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER bit 10-9 RTCCLKSEL<1:0>: RTCC Clock Select bits When a new value is written to these bits, the Seconds Value register should also be written to properly reset the clock prescalers in the RTCC. 11 = Reserved 10 = Reserved 01 = RTCC uses the external 32.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-2: Bit Range 31:24 23:16 15:8 7:0 RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (2) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-2: RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(2) 11111111 = Alarm will trigger 256 times bit 7-0 • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x R/W-x U-0 U-0 U
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x R/W-x YEAR01<3:0> R/W-x R/W-x R/W-x MONTH10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x R/W-x U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x MONTH10<3:0> R/W-x R/W-x U-0 U-0 — — Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x R/W-x U-0 U-0 R/W-x R/W-x — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: CRYPTO ENGINE Bulk ciphers that are handled by the Crypto Engine include: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49.
Crypto Engine Control Registers Virtual Address (BF8E_#) Register Name TABLE 26-2: 5000 CEVER CRYPTO ENGINE REGISTER MAP 5004 CECON 5008 CEBDADDR 500C 5010 CEBDPADDR CESTAT Preliminary 5014 CEINTSRC 5018 CEINTEN 501C CEPOLLCON 5020 5024 Legend: CEHDLEN CETRLLEN 31/15 30/14 29/13 31:16 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 REVISION<7:0> 20/4 19/3 18/2 17/1 16/0 VERSION<7:0> 15:0 0000 ID<15:0> 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 CEVER: CRYPTO ENGINE REVISION, VERSION, AND ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REVISION<7:0> R-0 R-0 R-0 R-0 R-0 VERSION<7:0> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ID<15:8> ID<7:0> Legend: R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-2: Bit Range 31:24 23:16 15:8 7:0 CECON: CRYPTO ENGINE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0, HC R/W-0 U-0 U-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-3: Bit Range 31:24 23:16 15:8 7:0 CEBDADDR: CRYPTO ENGINE BUFFER DESCRIPTOR REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BDPADDR<31:24> R-0 R-0 R-0 R-0 R-0 BDPADDR<23:16> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BDPADDR<15:8> R-0 R-0 BDPADDR<7:0> L
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-5: Bit Range 31:24 CESTAT: CRYPTO ENGINE STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 R-0 R-0 R-0 R-0 ERRMODE<2:0> 23:16 15:8 U-0 U-0 — — R-0 R-0 Bit 27/19/11/3 Bit 26/18/10/2 R-0 R-0 ERROP<2:0> R-0 R-0 R-0 R-0 R-0 Bit 24/16/8/0 R-0 R-0 ERRPHASE<1:0> R-0 R-0 R-0 START ACTIVE R-0 R-0 R-0 R-0 R-0 R-0 BDSTATE<3:0> R-0 Bit 25/17/9/1 BDCTRL<15:8> R-0 7:0 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-5: bit 16 bit 15-0 CESTAT: CRYPTO ENGINE STATUS REGISTER (CONTINUED) ACTIVE: Buffer Descriptor Processor Status bit 1 = BDP is active 0 = BDP is idle BDCTRL<15:0>: Descriptor Control Word Status bits These bits contain the Control Word for the current Buffer Descriptor. 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-6: Bit Range 31:24 23:16 15:8 7:0 CEINTSRC: CRYPTO ENGINE INTERRUPT SOURCE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-7: Bit Range 31:24 23:16 15:8 7:0 CEINTEN: CRYPTO ENGINE INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-8: Bit Range 31:24 23:16 15:8 7:0 CEPOLLCON: CRYPTO ENGINE POLL CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-9: Bit Range 31:24 23:16 15:8 7:0 CEHDLEN: CRYPTO ENGINE HEADER LENGTH REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 26.2 Crypto Engine Buffer Descriptors Host software creates a linked list of buffer descriptors and the hardware updates them. Table 26-3 provides a list of the Crypto Engine buffer descriptors, followed by format descriptions of each buffer descriptor (see Figure 26-2 through Figure 26-9).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 26-2: FORMAT OF BD_CTRL Bit Range Bit 31/23/15/7 Bit 30/22/14/6 31-24 DESC_EN 23-16 — — SA_ FETCH_EN Bit 29/21/13/5 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 CRY_MODE<2:0> — — LIFM — PKT_ INT_EN — CBD_ INT_EN — Bit 28/20/12/4 Bit 27/19/11/3 LAST_BD 15-8 BD_BUFLEN<15:8> 7-0 BD_BUFLEN<7:0> bit 31 DESC_EN: Descriptor Enable 1 = The descriptor is owned by hardware.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 26-4: Bit Range FORMAT OF BD_SRCADDR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31-24 BD_SCRADDR<31:24> 23-16 BD_SCRADDR<23:16> 15-8 BD_SCRADDR<15:8> 7-0 BD_SCRADDR<7:0> bit 31-0 FORMAT OF BD_DSTADDR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31-24 BD_DSTADDR<31:24> 23-16 BD_DSTADDR<23:16> 15-8 BD_DSTADDR<15:8> 7-0 BD
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 26-7: Bit Range FORMAT OF BD_UPDPTR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31-24 BD_UPDADDR<31:24> 23-16 BD_UPDADDR<23:16> 15-8 BD_UPDADDR<15:8> 7-0 BD_UPDADDR<7:0> bit 31-0 FORMAT OF BD_MSG_LEN Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31-24 MSG_LENGTH<31:24> 23-16 MSG_LENGTH<23:16> 15-8 MSG_LENGTH<15:8> 7-0 MSG
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 26.3 Security Association Structure Table 26-4 shows the Security Association Structure. The Crypto Engine uses the Security Association to determine the settings for processing a Buffer Descriptor Processor.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 26-4: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED) Bit 31/23/15/7 Name SA_ENCKEY3 SA_ENCKEY4 SA_ENCKEY5 SA_ENCKEY6 SA_ENCKEY7 SA_ENCKEY8 SA_AUTHIV1 SA_AUTHIV2 SA_AUTHIV3 SA_AUTHIV4 SA_AUTHIV5 SA_AUTHIV6 SA_AUTHIV7 SA_AUTHIV8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 23:16 ENCKEY<23:16> 15:8 ENCKEY<15:8> 7:0 31:24 ENCKEY<7:0> ENCKEY<31:24> 23:16 ENCKEY<23:16> 15:8 ENCKEY<15:8>
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 26-4: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED) Bit 31/23/15/7 Name SA_ENCIV1 SA_ENCIV2 SA_ENCIV3 SA_ENCIV4 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 31:24 ENCIV<31:24> 23:16 ENCIV<23:16> 15:8 7:0 ENCIV<15:8> ENCIV<7:0> 31:24 ENCIV<31:24> 23:16 ENCIV<23:16> 15:8 7:0 ENCIV<15:8> ENCIV<7:0> 31:24 ENCIV<31:24> 23:16 ENCIV<23:16> 15:8 7:0 ENCIV<15:8> ENCIV<7:0> 31:24 ENCIV<31:24
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Figure 26-10 shows the Security Association control word structure. The Crypto Engine fetches different structures for different flows and ensures that hardware fetches minimum words from SA required for processing. The structure is ready for hardware optimal data fetches.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Figure 26-10: Format of SA_CTRL (Continued) bit 16-10 ALGO<6:0>: Type of Algorithm to Use 1xxxxxx = HMAC 1 x1xxxxx = SHA-256 xx1xxxx = SHA1 xxx1xxx = MD5 xxxx1xx = AES xxxxx1x = TDES xxxxxx1 = DES bit 9 ENC: Type of Encryption Setting 1 = Encryption 0 = Decryption bit 8-7 KEYSIZE<1:0>: Size of Keys in SA_AUTHKEYx or SA_ENCKEYx 11 = Reserved; do not use 10 = 256 bits 01 = 192 bits 00 = 128 bits(1) bit 6-4 MULTITASK<2:0>: How to Combine P
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 27.0 Note: RANDOM NUMBER GENERATOR (RNG) TABLE 27-1: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
RNG Control Registers Virtual Address (BF8E_#) Register Name TABLE 27-2: 6000 RNGVER 6004 6008 600C RANDOM NUMBER GENERATOR (RNG) REGISTER MAP RNGCON RNGPOLY1 RNGPOLY2 6010 RNGNUMGEN1 Preliminary 6014 RNGNUMGEN2 6018 601C 6020 Legend: RNGSEED1 RNGSEED2 RNGCNT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ID<15:0> 15:0 xxxx VERSION<7:0> REVISION<7:0> 31:16 — — — — — — 15:0 — — — LOAD TRNGMODE CONT — — — — — PR
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-1: Bit Range 31:24 23:16 15:8 7:0 RNGVER: RANDOM NUMBER GENERATOR VERSION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ID<15:8> R-0 R-0 R-0 R-0 ID<7:0> R-0 R-0 R-0 R-0 R-0 R-0 R-0 VERSION<7:0> R-0 R-0 REVISION<7:0> Legend: R = Read
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-2: Bit Range 31:24 23:16 15:8 7:0 RNGCON: RANDOM NUMBER GENERATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — LOAD TRNGMODE CONT PRNGEN TRNG
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-3: Bit Range 31:24 23:16 15:8 7:0 RNGPOLYx: RANDOM NUMBER GENERATOR POLYNOMIAL REGISTER ‘x’ (‘x’ = 1 OR 2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POLY<31:24> R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 POLY<23:16> R/W-0 R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-5: Bit Range 31:24 23:16 15:8 7:0 RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER ‘x’ (‘x’ = 1 OR 2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SEED<31:24> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SEED<23:16> R-0 R-0 SEED<15:8> R-0 R-0 R-0 R-0 R-0 S
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 28.0 Note: 12-BIT HIGH-SPEED SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TODIGITAL CONVERTER (ADC) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 22.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 28-1: AN0 AN45 N/C N/C ADC BLOCK DIAGRAM 00 01 10 11 AVDD VREF+ VREFADCSEL<1:0> 00 10 11 CONCLKDIV<5:0> VREFSEL<2:0> 0 1 VREFH DIFF0<1> (ADCIMCON1<1>) VREFL TAD0-TAD4 ADCDIV<6:0> (ADCxTIME<22:16>) TQ ADC0 TAD7 AN4 AN49 N/C N/C 01 TCLK SH0ALT<1:0> (ADCTRGMODE<17:16>) AN5 VREFL AVSS ADCDIV<6:0> (ADCCON2<6:0>) 00 01 10 11 SH4ALT<1:0> (ADCTRGMODE<25:24>) AN9 VREFL 0 1 ADC4 DIFF4<1> (ADCIMCON1<1>) AN5 AN41 IVR
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 28-2: S&H BLOCK DIAGRAM ADC3 ADC0 AN0 00 AN3 00 AN45 01 AN48 01 N/C 10 N/C 10 N/C 11 N/C 11 SAR SAR SH3ALT<1:0> (ADCTRGMODE<23:22) SH0ALT<1:0> (ADCTRGMODE<17:16) AN5 0 AN8 0 VREFL 1 VREFL 1 DIFF3<1> (ADCIMCON1<7>) DIFF0<1> (ADCIMCON1<1>) ADC4 ADC1 AN1 00 AN4 00 AN46 01 AN49 01 N/C 10 N/C 10 N/C 11 N/C 11 SAR SAR SH1ALT<1:0> (ADCTRGMODE<19:18) SH4ALT<1:0> (ADCTRGMODE<25:24) AN6 0 AN9 0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 28-3: FIFO BLOCK DIAGRAM ADCID<2:0> (ADCFSTAT<2:0>) ADCx ID FEN (ADCFSTAT<31>) ADC4 DATA<31:0> ADCFIFO ADC4EN (ADCFSTAT<28>) ADCx ID Converted Data FIFO (16 Words) If data available in FIFO FRDY (ADCFSTAT<22>) FIEN (ADCFSTAT<23>) Interrupt ADC0EN (ADCFSTAT<24>) FCNT<7:0> (ADCFSTAT<15:8>) Number of data in FIFO ADC0 DS60001320B-page 432 Preliminary 2015 Microchip Technology Inc.
ADC Control Registers ADC REGISTER MAP Register Name B000 ADCCON1 B004 ADCCON2 31/15 30/14 31:16 TRBEN TRBERR 15:0 ON — SIDL REFFLT EOSRDY 31:16 BGVRRDY 29/13 31:16 EOSIEN — 26/10 25/9 24/8 TRBSLV<2:0> CVDEN FSSCLKEN FSPBCLKEN FRACT — 22/6 ADCEIOVR 21/5 20/4 19/3 SELRES<1:0> — 18/2 17/1 16/0 — — STRGSRC<4:0> IRQVS<2:0> STRGLVL — 0060 SAMC<9:0> — ADCEIS<2:0> TRGSUSP UPDIEN UPDRDY SAMP RQCNVRT — GLSWTRG GSWTRG SH3ALT<1:0> — DIGEN4 DIGEN3 0000 DIGEN2 DI
Register Name B04C ADCCMP3 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 DCMPHI<15:0> 15:0 DCMPLO<15:0> B050 ADCCMPEN4 31:16 CMPE31(1) CMPE30(1) B054 ADCCMP4 31:16 DCMPHI<15:0> 15:0 DCMPLO<15:0> 15:0 CMPE15 CMPE14 CMPE29(1) CMPE28(1) CMPE27(1) CMPE26(1) CMPE25(1) CMPE24(1) CMPE13 CMPE12 CMPE11 CMPE10 CMPE9 CMPE8 31:16 CMPE31(1) CMPE30(1) B05C ADCCMP5 31:16 DCMPHI<15:0> 15:0 DCMPLO<15:0> CMPE15 CMPE14 CMPE28(1) CMPE27(1) CMPE26(1) CMPE25(1) CMPE24(1
Register Name 31/15 30/14 29/13 28/12 27/11 B0AC ADCCMPCON4 31:16 — — — — — 15:0 — — — B0B0 ADCCMPCON5 31:16 — — — 15:0 — — — B0B4 ADCCMPCON6 31:16 — — — 15:0 — — — 31:16 FEN — — B0B8 ADCFSTAT B0C0 ADCBASE 25/9 24/8 — — — AINID<4:0> — — — — — — — — ADC3EN ADC2EN ADC1EN FCNT<7:0> — — — — — Preliminary B0D4 ADC0TIME B0D8 ADC1TIME B0DC ADC2TIME B0E0 ADC3TIME B0E4 ADC4TIME B0F0 ADCEIEN1 B0F4 ADCEIEN2 B0F8 ADCEISTAT1 B0FC ADCEISTAT2 DS60001320B-page 4
Register Name B188 ADC2CFG 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range Virtual Address (BF84_#) ADC REGISTER MAP (CONTINUED) 31:16 ADCCFG<31:16> 0000 15:0 ADCCFG<15:0> 0000 31:16 ADCCFG<31:16> 0000 15:0 ADCCFG<15:0> 0000 31:16 ADCCFG<31:16> 0000 15:0 ADCCFG<15:0> 0000 31:16 ADCCFG<31:16> 0000 15:0 ADCCFG<15:0> 0000 B1C0 ADCSYSCFG0 31:16 AN<31:16> xxxF 15:0 AN<15:0> B18C ADC3CFG B190 ADC4CFG
Register Name B234 ADCDATA13 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range Virtual Address (BF84_#) ADC REGISTER MAP (CONTINUED) 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0
Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range Virtual Address (BF84_#) ADC REGISTER MAP (CONTINUED) Preliminary B280 ADCDATA32(1) 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 B284 ADCDATA33(1) 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 B288 ADCDATA34(1) 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 B28C ADCDATA35(2) 31:16 DATA<31:16> 0000 15:0 DATA<15:0> 0000 B290 ADCDATA36(2) 31:16 D
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-1: Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 31:24 23:16 R/W-0 R-0, HS, HC TRBEN TRBERR R/W-0 R/W-1 FRACT R/W-0 15:8 U-0 bit 30 U-0 R/W-0 — Legend: R = Readable bit -n = Value at POR Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 R/W-1 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 TRBMST<2:0> TRBSLV<2:0> R/W-0 SELRES<1:0> ON 7:0 bit 31 ADCCON1: ADC CONTROL REGI
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-1: ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 20-16 STRGSRC<4:0>: Scan Trigger Source Select bits 11111 = Reserved • • • bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-7 bit 6-4 01101 = Reserved 01100 = Comparator 2 (COUT) 01011 = Comparator 1 (COUT) 01010 = OCMP5 01001 = OCMP3 01000 = OCMP1 00111 = TMR5 match 00110 = TMR3 match 00101 = TMR1 match 00100 = INT0 External interrupt 00011 = Reserved 00010 = Globa
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-1: bit 3 bit 2-0 ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED) STRGLVL: Scan Trigger High Level/Positive Edge Sensitivity bit 1 = Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the ADCTRGx register), the scan trigger will continue for all selected analog inputs, until the STRIG option is removed. 0 = Scan trigger is positive edge sensitive.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-2: Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R-0, HS, HC R-0, HS, HC R-0, HS, HC R/W-0 R/W-0 BGVRRDY REFFLT EOSRDY R/W-0 R/W-0 R/W-0 23:16 15:8 ADCCON2: ADC CONTROL REGISTER 2 Bit Bit 26/18/10/2 25/17/9/1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CVDCPL<2:0> R/W-0 R/W-0 SAMC<9:8> SAMC<7:0> R/W-0 R/W-0 R/W-0 R/W-0 BGVRIEN REFFLTI
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-2: ADCCON2: ADC CONTROL REGISTER 2 (CONTINUED) bit 14 REFFLTIEN: Band Gap/VREF Voltage Fault Interrupt Enable bit 1 = Interrupt will be generated when the REFFLT bit is set 0 = No interrupt is generated when the REFFLT bit is set bit 13 EOSIEN: End of Scan Interrupt Enable bit 1 = Interrupt will be generated when EOSRDY bit is set 0 = No interrupt is generated when the EOSRDY bit is set bit 12 ADCEIOVR: Early Interrupt Req
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-3: Bit Range ADCCON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DIGEN1 31:24 ADCSEL<1:0> R/W-0 23:16 15:8 U-0 U-0 R/W-0 R/W-0 DIGEN7 — — DIGEN4 DIGEN3 DIGEN2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC TRGSUSP UPDIEN UPDRDY R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-3: bit 18 ADCCON3: ADC CONTROL REGISTER 3 (CONTINUED) DIGEN2: ADC2 Digital Enable bit 1 = ADC2 is digital enabled 0 = ADC2 is digital disabled bit 17 DIGEN1: ADC1 Digital Enable bit 1 = ADC1 is digital enabled 0 = ADC1 is digital disabled bit 16 DIGEN0: ADC0 Digital Enable bit 1 = ADC0 is digital enabled 0 = ADC0 is digital disabled bit 15-13 VREFSEL<2:0>: Voltage Reference (VREF) Input Selection bits VREFSEL<2:0> 1xx 011 010
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-3: ADCCON3: ADC CONTROL REGISTER 3 (CONTINUED) bit 6 GSWTRG: Global Software Trigger bit 1 = Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0> bits in the ADCCON1 register 0 = Do not trigger an analog-to-digital conversion Note: This bit is automatically cleared in the next ADC clock cycl
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-4: ADCTRGMODE: ADC TRIGGERING MODE FOR DEDICATED ADC REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SH3ALT<1:0> SH2ALT<1:0> SH4ALT<1:0> R/W-0 SH1ALT<1:0> R/W-0 SH0ALT<1:0> U-0 U-0 U-0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-4: ADCTRGMODE: ADC TRIGGERING MODE FOR DEDICATED ADC REGISTER bit 9 STRGEN1: ADC1 Presynchronized Triggers bit 1 = ADC1 uses presynchronized triggers 0 = ADC1 does not use presynchronized triggers bit 8 STRGEN0: ADC0 Presynchronized Triggers bit 1 = ADC0 uses presynchronized triggers 0 = ADC0 does not use presynchronized triggers bit 7-5 bit 4 Unimplemented: Read as ‘0’ SSAMPEN4: ADC4 Synchronous Sampling bit 1 = ADC4 uses
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-5: Bit Range 31:24 23:16 15:8 7:0 ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DIFF15 SIGN15 DIFF14 SIGN14 DIFF13 SIGN13 DIFF12 SIGN12 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DIFF11 SIGN11 DIFF10 SIGN10 DIFF9 SIGN9 DI
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-5: ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1 (CONTINUED) bit 20 SIGN10: AN10 Signed Data Mode bit 1 = AN10 is using Signed Data mode 0 = AN10 is using Unsigned Data mode bit 19 DIFF9: AN9 Mode bit 1 = AN9 is using Differential mode 0 = AN9 is using Single-ended mode bit 18 SIGN9: AN9 Signed Data Mode bit 1 = AN9 is using Signed Data mode 0 = AN9 is using Unsigned Data mode bit 17 DIFF8: AN 8 Mode bit 1 = AN8 is using
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-5: ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1 (CONTINUED) bit 4 SIGN2: AN2 Signed Data Mode bit 1 = AN2 is using Signed Data mode 0 = AN2 is using Unsigned Data mode bit 3 DIFF1: AN1 Mode bit 1 = AN1 is using Differential mode 0 = AN1 is using Single-ended mode bit 2 SIGN1: AN1 Signed Data Mode bit 1 = AN1 is using Signed Data mode 0 = AN1 is using Unsigned Data mode bit 1 DIFF0: AN0 Mode bit 1 = AN0 is using Different
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-6: Bit Range 31:24 23:16 15:8 7:0 ADCIMCON2: ADC INPUT MODE CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DIFF31 (1) SIGN31 (1) DIFF30 (1) (1) SIGN30 DIFF29 (1) (1) SIGN29 DIFF28 (1) SIGN28(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DIFF27(1)
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-6: ADCIMCON2: ADC INPUT MODE CONTROL REGISTER 2 (CONTINUED) bit 21 DIFF26: AN26 Mode bit(1) 1 = AN26 is using Differential mode 0 = AN26 is using Single-ended mode bit 20 SIGN26: AN26 Signed Data Mode bit(1) 1 = AN26 is using Signed Data mode 0 = AN26 is using Unsigned Data mode bit 19 DIFF25: AN25 Mode bit(1) 1 = AN25 is using Differential mode 0 = AN25 is using Single-ended mode bit 18 SIGN25: AN25 Signed Data Mode bit
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-6: ADCIMCON2: ADC INPUT MODE CONTROL REGISTER 2 (CONTINUED) bit 6 SIGN19: AN19 Signed Data Mode bit(1) 1 = AN19 is using Signed Data mode 0 = AN19 is using Unsigned Data mode bit 5 DIFF18: AN18 Mode bit 1 = AN18 is using Differential mode 0 = AN18 is using Single-ended mode bit 4 SIGN18: AN18 Signed Data Mode bit 1 = AN18 is using Signed Data mode 0 = AN18 is using Unsigned Data mode bit 3 DIFF17: AN17 Mode bit 1 = AN17
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-7: Bit Range 31:24 23:16 15:8 7:0 ADCIMCON3: ADC INPUT MODE CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 SIGN44 — — — — — — DIFF44 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DIFF43 SIGN43 DIFF42(2) SIGN42(2) DIFF41(2) SIGN41(2) DIFF40(2) SIGN40(2) R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-7: ADCIMCON3: ADC INPUT MODE CONTROL REGISTER 3 (CONTINUED) bit 16 SIGN40: AN40 Signed Data Mode bit(2) 1 = AN40 is using Signed Data mode 0 = AN40 is using Unsigned Data mode bit 15 DIFF39: AN39 Mode bit(2) 1 = AN39 is using Differential mode 0 = AN39 is using Single-ended mode bit 14 SIGN39: AN39 Signed Data Mode bit(2) 1 = AN39 is using Signed Data mode 0 = AN39 is using Unsigned Data mode bit 13 DIFF38: AN38 Mode bit
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-7: ADCIMCON3: ADC INPUT MODE CONTROL REGISTER 3 (CONTINUED) bit 1 DIFF32: AN32 Mode bit(1) 1 = AN32 is using Differential mode 0 = AN32 is using Single-ended mode bit 0 SIGN32: AN32 Signed Data Mode bit(1) 1 = AN32 is using Signed Data mode 0 = AN32 is using Unsigned Data mode Note 1: 2: This bit is not available on 64-pin devices. This bit is not available on 64-pin and 100-pin devices. 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-8: ADCGIRQEN1: ADC GLOBAL INTERRUPT ENABLE REGISTER 1 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AGIEN31(1) AGIEN30(1) AGIEN29(1) AGIEN28(1) AGIEN27(1) AGIEN26(1) AGIEN25(1) AGIEN24(1) 23:16 AGIEN23(1) AGIEN22(1) AGIEN21(1) AGIEN20(1) AGIEN19(1) 15:8 7:0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-10: ADCCSS1: ADC COMMON SCAN SELECT REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 R/W-0 R/W-0 R/W-0 R/W-0 CSS31 (1) CSS30 (1) CSS29 (1) CSS28 (1) Bit 27/19/11/3 R/W-0 (1) Bit 25/17/9/1 R/W-0 R/W-0 (1) (1) Bit 24/16/8/0 R/W-0 (1) CSS26 CSS25 R/W-0 R/W-0 R/W-0 CSS18 CSS17 CSS16 R/W-0 R/W-0 R/W-0 R/W-0 CSS12 CSS11 CSS10 CSS9 CSS8 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-11: ADCCSS2: ADC COMMON SCAN SELECT REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CSS44 CSS43 CSS42(2) CSS41(2) R/W-0 R/W-0 R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-12: ADCDSTAT1: ADC DATA READY STATUS REGISTER 1 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) 23:16 15:8 7:0 ARDY31 R-0, HS, HC (1) ARDY23 R-0, HS, HC ARDY30 R-0, HS, HC (1) ARDY22 R-0, HS, H
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-14: ADCCMPENx: ADC DIGITAL COMPARATOR ‘x’ ENABLE REGISTER (‘x’ = 1 THROUGH 6) Bit Bit Range 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMPE31(1) CMPE30(1) CMPE29(1) CMPE28(1) CMPE27(1) CMPE26(1) CMPE25(1) CMPE24(1) 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMP
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-15: ADCCMPx: ADC DIGITAL COMPARATOR ‘x’ LIMIT VALUE REGISTER (‘x’ = 1 THROUGH 6) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 bit 15-0 Note 1: 2: 3: Bit Bit 27/19/11/3 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCMPHI<15:8>(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCMPHI<7:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-16: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER (‘x’ = 1 THROUGH 6) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 R/W-0 R/W-0 R/W-0 R/W-0 AFEN DATA16EN DFMODE U-0 U-0 U-0 — — — R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC Bit Bit 27/19/11/3 26/18/10/2 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R-0, HS, HC AFG
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-16: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER (‘x’ = 1 THROUGH 6) bit 24 AFRDY: Digital Filter ‘x’ Data Ready Status bit 1 = Data is ready in the FLTRDATA<15:0> bits 0 = Data is not ready Note: This bit is cleared by reading the FLTRDATA<15:0> bits or by disabling the Digital Filter module (by setting AFEN to ‘0’).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-17: ADCTRG1: ADC TRIGGER SOURCE 1 REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — TRGSRC3<4:0> R/W-0 TRGSRC2<4:0> R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-18: ADCTRG2: ADC TRIGGER SOURCE 2 REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 U-0 U-0 R/W-0 R/W-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — 31:24 23:16 15:8 7:0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC7<4:0> R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-19: ADCTRG3: ADC TRIGGER SOURCE 3 REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 U-0 U-0 R/W-0 R/W-0 — — — U-0 U-0 U-0 R/W-0 R/W-0 — — — U-0 U-0 U-0 R/W-0 R/W-0 — — — 31:24 23:16 15:8 7:0 TRGSRC11<4:0> R/W-0 R/W-0 R/W-0 TRGSRC10<4:0> R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-20: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC 31:24 CVDDATA<15:8> R-0, HS, HC 23:16 R-0, HS, HC R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-20: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL REGISTER bit 3 bit 2 bit 1 bit 0 IEHIHI: High/High Digital Comparator 0 Event bit 1 = Generate a Digital Comparator 0 Event when DCMPHI<15:0> DATA<31:0> 0 = Do not generate an event IEHILO: High/Low Digital Comparator 0 Event bit 1 = Generate a Digital Comparator 0 Event when DATA<31:0> < DCMPHI<15:0> 0 = Do not generate an event IELOHI: Low/High Digital Comparator 0 Event bi
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-21: ADCCMPCONx: ADC DIGITAL COMPARATOR ‘x’ CONTROL REGISTER (‘x’ = 2 THROUGH 6) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — — — — — — U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, H
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-21: ADCCMPCONx: ADC DIGITAL COMPARATOR ‘x’ CONTROL REGISTER (‘x’ = 2 THROUGH 6) (CONTINUED) bit 1 bit 0 IELOHI: Low/High Digital Comparator ‘x’ Event bit 1 = Generate a Digital Comparator ‘x’ Event when the DCMPLO<15:0> bits DATA<31:0> bits 0 = Do not generate an event IELOLO: Low/Low Digital Comparator ‘x’ Event bit 1 = Generate a Digital Comparator ‘x’ Event when the DATA<31:0> bits < DCMPLO<15:0> bits 0 = Do not generate
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-22: ADCFSTAT: ADC FIFO STATUS REGISTER Bit Range Bit Bit 31/23/15/7 30/22/14/6 R/W-0 31:24 23:16 15:8 Bit 29/21/13/5 Bit 28/20/12/4 U-0 R/W-0 R/W-0 U-0 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 FEN — — ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN R/W-0 R-0, HS, HC R-0, HS, HC U-0 U-0 U-0 U-0 U-0 FIEN FRDY FWROVERR — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-23: ADCFIFO: ADC FIFO DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 R-0 R-0 R-0 R-0 Bit Bit 27/19/11/3 26/18/10/2 R-0 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA<31:24> R-0 R-0 R-0 R-0 R-0 DATA<23:16> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA<15:8> R-0 DATA<7:0> Legend: R = Readable bit W = Writ
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-24: ADCBASE: ADC BASE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCBASE<15:8> R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-25: ADCDATAx: ADC OUTPUT DATA REGISTER (‘x’ = 0 THROUGH 44) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Bit Bit 27/19/11/3 26/18/10/2 R-0 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA<31:24> R-0 DATA<23:16> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA<15:8> R-0 DATA<7:0> Legend: R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-26: ADCTRGSNS: ADC TRIGGER LEVEL/EDGE SENSITIVITY REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — LVL11 LVL10 LVL9 LVL8 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-27: ADCxTIME: DEDICATED ADCx TIMING REGISTER ‘x’ (‘x’ = 0 THROUGH 4) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 R/W-0 — — — U-0 R/W-0 R/W-0 31:24 23:16 7:0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-1 R/W-1 SELRES<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCDIV<6:0> U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC<
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-28: ADCEIEN1: ADC EARLY INTERRUPT ENABLE REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EIEN31 (1) (1) EIEN30 EIEN29 (1) EIEN28 (1) EIEN27 (1) EIEN26 (1) EIEN25 (1) EIEN24(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EIEN23(1
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-30: ADCEISTAT1: ADC EARLY INTERRUPT STATUS REGISTER 1 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) R-0, HS, HC (1) 23:16 15:8 7:0 EIRDY31 R-0, HS, HC (1) EIRDY23 R-0, HS, HC EIRDY30 R-0, HS, HC (1) EIRDY22
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-31: ADCEISTAT2: ADC EARLY INTERRUPT STATUS REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R-0, HS, HC (2) R-0, HS, HC (2) R-0, HS, HC (2) R-0, HS, HC (2) R-0, HS, H
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-32: ADCANCON: ADC ANALOG WARM-UP CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 31:24 23:16 15:8 7:0 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 WKUPCLKCNT<3:0> R/W-0 R/W-0 R/W-0 WKIEN7 — — WKIEN4 WKIEN3 WKIEN2 WKIEN1 WKIEN0 R-0, HS, HC U-0 U-0 R-0, HS, HC R-0, HS,
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-32: ADCANCON: ADC ANALOG WARM-UP CONTROL REGISTER (CONTINUED) bit 7 ANEN7: Shared ADC (ADC7) Analog and Bias Circuitry Enable bit 1 = Analog and bias circuitry enabled. Once the analog and bias circuit is enabled, the ADC module needs a warm-up time, as defined by the WKUPCLKCNT<3:0> bits.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-33: ADCxCFG: ADCx CONFIGURATION REGISTER ‘x’ (‘x’ = 1 THROUGH 4 AND 7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCCFG<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCCFG<23:16>
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 28-34: ADCSYSCFG1: ADC SYSTEM CONFIGURATION REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 R-y R-y R-y R-y R-y R-y R-y R-y Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-y R-y R-y R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-y AN<31:23> R-y AN<23:16> R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 AN<15:8> AN<7:0> Legend: y = POR value i
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 486 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 29.0 Note: CONTROLLER AREA NETWORK (CAN) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. “Controller Area Network (CAN)” (DS60001154) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
CAN Control Registers Note: The ‘i’ shown in register names denotes CAN1 or CAN2. Register Name(1) Preliminary Virtual Address (BF88_#) TABLE 29-1: 0000 C1CON 0010 C1CFG 0020 C1INT 0030 C1VEC 0040 C1TREC 0050 C1FSTAT 0060 C1RXOVF 0070 C1TMR 0080 C1RXM0 C1RXM1 00A0 C1RXM2 2015 Microchip Technology Inc.
Virtual Address (BF88_#) CAN1 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES (CONTINUED) 00F0 C1FLTCON3 0100 C1FLTCON4 0110 C1FLTCON5 0120 C1FLTCON6 0130 C1FLTCON7 Preliminary 01400330 C1RXFn (n = 0-31) 0340 C1FIFOBA C1FIFOINTn (n = 0) 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000 15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0>
Virtual Address (BF88_#) Register Name(1) 1000 C2CON 1010 C2CFG 1040 1050 Preliminary 1060 1070 1080 10A0 10B0 10B0 C2INT C2VEC C2TREC C2FSTAT C2RXOVF C2TMR C2RXM0 C2RXM1 C2RXM2 C2RXM3 1010 C2FLTCON0 2015 Microchip Technology Inc.
Virtual Address (BF88_#) 1110 C2FLTCON5 1120 C2FLTCON6 1130 C2FLTCON7 1340 C2RXFn (n = 0-31) C2FIFOBA Preliminary C2FIFOINTn (n = 0) 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000 31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000 15:0 FLTEN21 MSEL21<1:0> FSEL
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-1: Bit Range 31:24 23:16 15:8 7:0 CiCON: CAN MODULE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 S/HC-0 R/W-1 — — — — ABAT R-0 R-0 R-1 OPMOD<2:0> R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 REQOP<2:0> R/W-0 U-0 U-0 U-0 CANCAP — — — U-0 — U-0 R-0 U-0 U-0 U-0 U-0 R/W-0 ON(1) — SIDLE — CANBUSY — — — U
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-1: CiCON: CAN MODULE CONTROL REGISTER (CONTINUED) bit 13 SIDLE: CAN Stop in Idle bit 1 = CAN Stops operation when system enters Idle mode 0 = CAN continues operation when system enters Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 CANBUSY: CAN Module is Busy bit 1 = The CAN module is active 0 = The CAN module is completely disabled bit 10-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: Device Net Filter Bit Numbe
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-2: Bit Range 31:24 23:16 15:8 7:0 CiCFG: CAN BAUD RATE CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — WAKFIL — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) SEG2PHTS R/W-0 SAM (2) R/W-0 S
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED) bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4) 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3) 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/TPBCLK5 111110 = TQ = (2 x 63)/TPBCLK5 • • • 000001 =
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 CiINT: CAN INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — MODIE CTMRIE RBIE TBIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 SERRIF
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED) bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = A bus wake-up activity interrupt has occurred 0 = A bus wake-up activity interrupt has not occurred bit 13 CERRIF: CAN Bus Error Interrupt Flag bit 1 = A CAN bus error has occurred 0 = A CAN bus error has not occurred bit 12 SERRIF: System Error Interrupt Flag bit 1 = A system error occurred (typically an illegal addr
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-4: Bit Range 31:24 23:16 15:8 7:0 CiVEC: CAN INTERRUPT CODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — — — U-0 R-1 R-0 FILHIT<4:0> R-0 ICODE<
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-5: Bit Range 31:24 23:16 15:8 7:0 CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWARN RXWARN EWARN R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-7: Bit Range 31:24 23:16 15:8 7:0 CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOV
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-9: Bit Range 31:24 23:16 15:8 7:0 CiRXMN: CAN ACCEPTANCE FILTER MASK ‘n’ REGISTER (‘n’ = 0-3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 SID<10:3> R/W-0 R/W-0 R/W-0 U-0 SID<2:0> R/W-0 — MIDE — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EID<17:16> R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN3 R/W-0 FLTEN2 R/W-0 FLTEN1 R/W-0 FLTEN0 MSEL3<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL2<4:0> R/W-0 MSEL1<1:0> R/W-0 B
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED) bit 15 FLTEN1: Filter 1 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL1<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Messag
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN7 R/W-0 FLTEN6 R/W-0 FLTEN5 R/W-0 FLTEN4 MSEL7<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL6<4:0> MSEL5<1:0> R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED) bit 15 FLTEN5: Filter 17 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL5<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN11 R/W-0 FLTEN10 R/W-0 FLTEN9 R/W-0 FLTEN8 MSEL11<1:0> R/W-0 FSEL11<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED) bit 15 FLTEN9: Filter 9 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL9<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Messag
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN15 R/W-0 FLTEN14 R/W-0 FLTEN13 R/W-0 FLTEN12 MSEL15<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL14<4:0> R/W-0 MSEL13<1:0> R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED) bit 15 FLTEN13: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL13<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = M
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family ,4 REGISTER 29-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN19 R/W-0 FLTEN18 R/W-0 FLTEN17 R/W-0 FLTEN16 MSEL19<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL18<4:0> R/W-0 MSEL17<1:0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED) bit 15 FLTEN17: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL17<1:0>: Filter 17 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL17<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = M
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN23 R/W-0 23:16 FLTEN22 R/W-0 15:8 FLTEN21 R/W-0 7:0 FLTEN20 MSEL23<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL22<4:0> R/W-0 MSEL21<1:0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED) bit 15 FLTEN21: Filter 21 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL21<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = M
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN27 R/W-0 FLTEN26 R/W-0 FLTEN25 R/W-0 FLTEN24 MSEL27<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL26<4:0> R/W-0 MSEL25<1:0> R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED) bit 15 FLTEN25: Filter 25 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL25<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Mes
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN31 R/W-0 FLTEN30 R/W-0 FLTEN29 R/W-0 FLTEN28 MSEL31<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL30<4:0> R/W-0 MSEL29<1:0> R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED) bit 15 FLTEN29: Filter 29 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL29<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Mes
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-18: CiRXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER 7 (‘n’ = 0-31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 R/W-x R/W-x SID<10:3> R/W-x R/W-x R/W-x U-0 SID<2:0> R/W-0 — EXID — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<17:16> R/W-x R/W-x
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0(1) CiFIFOBA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (‘n’ = 0-31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 S/HC-0 S/HC-0 U-0 U-0 FSIZE<4:0>(1) R/W-0 DONLY U-0 (1) U-0 — FRESET UINC —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (‘n’ = 0-31) (CONTINUED) bit 6 TXABAT: Message Aborted bit(2) 1 = Message was aborted 0 = Message completed successfully bit 5 TXLARB: Message Lost Arbitration bit(3) 1 = Message lost arbitration while being sent 0 = Message did not loose arbitration while being sent bit 4 TXERR: Error Detected During Transmission bit(3) 1 = A bus error occured while the message was being sent 0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (‘n’ = 0-31) Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 TXEMPTYIE — — — — — TXNFULLIE TXHALFIE U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE U-0 U-0 U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (‘n’ = 0-31) (CONTINUED) bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is half full 0 = FIFO is > half full TXEN = 0: (FIFO configured as a Receive Buffer) Unused, reads ‘0’ bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 29-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (‘n’ = 0-31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-x R-x R-x Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-0(1) R-0(1) CiFIFOUAn<31:24> R-x R-x R-x R-x R-x CiFIFOUAn<23:16> R-x R-x R-x R-x R-x CiFIFOUAn<15:8> R-x R-x R-x R-x R-x CiFIFOUAn<7
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 30.0 ETHERNET CONTROLLER Note: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. “Ethernet Controller” (DS60001155) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Table 30-1, Table 30-2, Table 30-3 and Table 30-4 show four interfaces and the associated pins that can be used with the Ethernet Controller.
Ethernet Control Registers Virtual Address (BF88_#) Register Name(1) TABLE 30-5: 2000 ETHCON1 2010 ETHCON2 2020 2030 2040 2050 Preliminary 2060 2070 2080 2090 ETHERNET CONTROLLER REGISTER SUMMARY ETHTXST ETHRXST ETHHT0 ETHHT1 ETHPMM0 ETHPMM1 ETHPMCS ETHPMO 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 15:0 ON — SIDL — — — TXRTS RXEN 31:16 — — — — — — — — 15:0 — — — — — 31:16 20A0 ETHRXFC 20/4 19/3 18/2 17/1 16/0 AUTOFC — — MANFC — — — — — — — —
Virtual Address (BF88_#) ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — 2110 31:16 ETH FRMTXOK 15:0 — 2120 31:16 ETH SCOLFRM 15:0 — 2130 31:16 ETH MCOLFRM 15:0 — 2140 31:16 ETH FRMRXOK 15:0 — 31:16 — 2150 2160 ETH FCSERR Preliminary 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) Bit Range ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED) 22B0 EMAC1 MWTD 31:16 22C0 EMAC1 MRDD 31:16 22D0 EMAC1 MIND 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — LINKFAIL NOTVALID SCAN 2300 EMAC1 SA0(2) 31:16 — — — — — — — — — — — — — — — — 2310 EMAC1 SA1(2) 31:16 — — — 2320 EMAC1 SA2(2) 31:16 — — — Legend: Preliminary Note 31/15 30/14 29/13 28/12 27/11 26/10 25
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-1: Bit Range 31:24 23:16 15:8 7:0 ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ON — SIDL — — — TXRTS RXEN(1) R/W-0 U-0 U-0 R/W-0 U-0 U-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-1: bit 7 ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED) AUTOFC: Automatic Flow Control bit 1 = Automatic Flow Control enabled 0 = Automatic Flow Control disabled Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to automatically enable and disable the Flow Control, respectively.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-2: Bit Range Bit 31/23/15/7 31:24 23:16 15:8 7:0 ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-3: Bit Range 31:24 23:16 15:8 7:0 ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — TXSTADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<23:16> R/W-0 R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-5: Bit Range ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 HT<31:24> 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HT<23:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-7: Bit Range 31:24 ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 31-24 bit 23-16 bit 15-8 bit 7-0 Note 1:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-9: Bit Range 31:24 23:16 15:8 7:0 ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 Note 1: 2: U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMCS<15:8> R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit Bit 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HTEN MPEN — NOTPM R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER (CONTINUED) bit 7 bit 6 bit 5 bit 4 CRCERREN: CRC Error Collection Enable bit 1 = The received packet CRC must be invalid for the packet to be accepted 0 = Disable CRC Error Collection filtering This bit allows the user to collect all packets that have an invalid CRC.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 RXFWM<7:0> 15:8 7:0 U-0 — — — — — — — — R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 — R/W-0 TXBUSEIE(1
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — — — — — — U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — TXBUSE RXBUSE — — — EWMARK FW
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER bit 7 RXDONE: Receive Done Interrupt bit(2) 1 = RX packet was successfully received 0 = No interrupt pending This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 BUFCNT<7:0>(1) U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 U-0 U-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED) bit 6 TXBUSY: Transmit Busy bit(2,6) 1 = TX logic is receiving data 0 = TX logic is idle This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES STATISTICS REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MCOLF
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 SOFT RESET SIM RESET — — RE
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 25/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — EXCESS DFR BPNOBK OFF NOB
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER bit 6 VLANPAD: VLAN Pad Enable bit(1,2) 1 = The MAC will pad all short frames to 64 bytes and append a valid CRC 0 = The MAC does not perform padding of short frames bit 5 PADENABLE: Pad/CRC Enable bit(1,3) 1 = The MAC will pad all short frames 0 = The frames presented to the MAC have a valid length bit 4 CRCENABLE: CRC Enable1 bit 1 = The MAC will append a CRC
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY LIMIT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit Bit 26/18/10/2 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — — — — RESETRMII(1) — — SPEEDRMII(1)
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT CONFIGURATION REGISTER Bit Range Bit 31/23/15/7 31:24 23:16 15:8 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 RESETMGMT — — — — — — — U
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 30-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 31.0 COMPARATOR Note: Key features of the Analog Comparator module are: • • • • Differential inputs Rail-to-rail operation Selectable output polarity Selectable inputs: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference - Comparator voltage reference (CVREF) • Selectable interrupt generation This data sheet summarizes the features of the PIC32MZ EF family of devices.
Comparator Control Registers COMPARATOR REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF84_#) TABLE 31-1: C000 CM1CON 31:16 15:0 — ON — COE — CPOL — — — — — — — — — COUT — — EVPOL<1:0> — — — CREF — — — — — — CCH<1:0> 0000 00C3 C010 CM2CON 31:16 15:0 — ON — COE — CPOL — — — — — — — — — COUT — — EVPOL<1:0> — — — CREF — — — — — — CCH<1:0> 0000 0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 31-1: Bit Range 31:24 23:16 15:8 7:0 CMxCON: COMPARATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — R/W-0 R/W-0 ON COE R/W-1 R/W-1 EVPOL<1:0> Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 — R/W-0 (1) CPOL Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 31-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 — —
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 32.0 Note: COMPARATOR VOLTAGE REFERENCE (CVREF) The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output.
Comparator Voltage Reference Control Registers COMPARATOR VOLTAGE REFERENCE REGISTER MAP 0E00 CVRCON Legend: Note 1: 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — ON — — — — — — — — — — — — — — — — — CVROE — CVRR — CVRSS — 18/2 17/1 — — CVR<3:0> 16/0 — All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 32-1: 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 32-1: Bit Range 31:24 23:16 15:8 7:0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 ON — — — — — — — U-0 R/W-0 R/W-0 R/W
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 576 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 33.0 Note: POWER-SAVING FEATURES Sleep mode includes the following characteristics: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “PowerSaving Features” (DS60001130) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 33.3 Peripheral Module Disable To disable a peripheral, the associated PMDx bit must be set to ‘1’. To enable a peripheral, the associated PMDx bit must be cleared (default). See Table 33-1 for more information. The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 33-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS(1) (CONTINUED) Peripheral PMDx bit Name Register Name and Bit Location UART3 U3MD PMD5<2> UART4 U4MD PMD5<3> UART5 U5MD PMD5<4> UART6 U6MD PMD5<5> SPI1 SPI1MD PMD5<8> SPI2 SPI2MD PMD5<9> SPI3 SPI3MD PMD5<10> SPI4 SPI4MD PMD5<11> SPI5 SPI5MD PMD5<12> SPI6 SPI6MD PMD5<13> I2C1 I2C1MD PMD5<16> I2C2 I2C2MD PMD5<17> I2C3 I2C3MD PMD5<18> I2C4 I2C4
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 33.3.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32MZ EF devices include two features to prevent alterations to enabled or disabled peripherals: • Control register lock sequence • Configuration bit select lock 33.3.1.
Virtual Address (BF80_#) Register Name(1) Preliminary 0040 PMD1 0050 PMD2 0060 PMD3 0070 PMD4 0080 PMD5 0090 PMD6 00A0 PMD7 PERIPHERAL MODULE DISABLE REGISTER SUMMARY Legend: Note 1: 31/15 30/14 29/13 31:16 — — 15:0 — — 31:16 — 16/0 All Resets Bit Range Bits 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 — — — — — — — — — — — — — — — CVRMD — — — — — — — — — — — ADCMD 0000 — — — — — — — — — — — — — — — 0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 582 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 34.0 Note: SPECIAL FEATURES The following run-time programmable Configuration registers provide additional configuration control: This data sheet summarizes the features of the PIC32MZ EF family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 32. “Configuration” (DS60001124) and Section 33.
Registers FFC0 DEVCFG3 FFC4 DEVCFG2 FFC8 DEVCFG1 FFCC DEVCFG0 FFD0 DEVCP3 FFD4 DEVCP2 Preliminary FFD8 DEVCP1 FFDC DEVCP0 FFE0 DEVSIGN3 FFE4 DEVSIGN2 FFE8 DEVSIGN1 FFEC DEVSIGN0 Legend: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY 31:16 31/15 30/14 — FUSBIDIO 29/13 28/12 27/11 IOL1WAY PMDL1WAY PGL1WAY 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — FETHIO FMIIEN — — — — — — — — — — — — FPLLODIV<2:0> xxxx — FPLLIDIV<2:0> xxxx 15:0 USERID<15:0> 31:16 — 1
FF44 ADEVCFG2 FF48 ADEVCFG1 FF4C ADEVCFG0 Preliminary FF50 ADEVCP3 FF54 ADEVCP2 FF58 ADEVCP1 FF5C ADEVCP0 FF60 ADEVSIGN3 FF64 ADEVSIGN2 FF68 ADEVSIGN1 FF6C ADEVSIGN0 31:16 31/15 30/14 — FUSBIDIO 29/13 28/12 27/11 IOL1WAY PMDL1WAY PGL1WAY 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — FETHIO FMIIEN — — — — — — — — — — — — 15:0 USERID<15:0> 31:16 — 15:0 — UPLLFSEL — — — — — FPLLMULT<6:0> 31:16 FDMTEN 15:0 — — — — OSCIOFNC — — — —
Register Name CFGCON 0020 DEVID 0030 SYSKEY 00C0 CFGEBIA(2) 00D0 CFGEBIC(2) CFGPG 31:16 — — 15:0 — — 31:16 29/13 28/12 27/11 26/10 25/9 — — — — DMAPRI — — IOLOCK PMDLOCK PGLOCK 24/8 23/7 22/6 CPUPRI — USBSSEN IOANCPEN VER<3:0> 21/5 20/4 — — — — ECCCON<1:0> 19/3 18/2 17/1 — — ICACLK JTAGEN TROEN — 16/0 OCACLK 0000 TDOEN DEVID<27:16> 15:0 DEVID<15:0> 31:16 xxxx 0000 SYSKEY<31:0> 15:0 31:16 EBIPINEN — — — — — — — 15:0 EBIA15EN EBIA14EN EBIA13EN
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-1: Bit Range 31:24 23:16 15:8 7:0 DEVSIGN0/ADEVSIGN0: DEVICE SIGNATURE WORD 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 r-0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 bit 29-22 bit 21 bit 20-19 bit 18 bit 17-16 bit 15 bit 14-12 bit 11 Note 1: Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit Bit 25/17/9/1 24/16/8/0 r-x R/P r-1 r-1 r-1 r-1 r-1 r-1 — EJTAGBEN — — — — — — R/P R/P R/P R/P r-1 r-1 R/P — — POSCBOOST R/P R/P SMCLR R/P POSCGAIN<1:0> R/P DBGPER<2:0> r-1 R/P R/
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-3: bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4-3 bit 2 bit 1-0 Note 1: DEVCFG0/ADEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) FSLEEP: Flash Sleep Mode bit 1 = Flash is powered down when the device is in Sleep mode 0 = Flash remains powered when the device is in Sleep mode FECCCON<1:0>: Dynamic Flash ECC Configuration bits Upon a device Reset, the value of these bits is copied to the ECCCON<1:0> bits (CFGCON<5:4>).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-4: Bit Range 31:24 DEVCFG1/ADEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/P R/P R/P FDMTEN 23:16 15:8 Bit 27/19/11/3 Bit 26/18/10/2 R/P R/P R/P DMTCNT<4:0> R/P R/P R/P FWDTEN WINDIS WDTSPGM R/P R/P FCKSM<1:0> 7:0 Bit 28/20/12/4 R/P R/P IESO FSOSCEN Legend: R = Readable bit -n = Value at POR R/P R/P R/P R/P R/P R/P R/P R/P WDTPS<4:0> r-1 r-1 r-1 R/P
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-4: DEVCFG1/ADEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All o
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-4: bit 2-0 DEVCFG1/ADEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) FNOSC<2:0>: Oscillator Selection bits 111 = FRC divided by FRCDIV<2:0> bits (FRCDIV) 110 = Reserved 101 = LPRC 100 = SOSC 011 = Reserved 010 = POSC (HS, EC) 001 = SPLL 000 = FRC divided by FRCDIV<2:0> bits (FRCDIV) DS60001320B-page 592 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-5: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2/ADEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 R/P r-1 r-1 r-1 r-1 r-1 r-1 — UPLLFSEL — — — — — — R/P R/P R/P r-1 r-1 r-1 r-1 r-1 — — — — — r-1 R/P R/P R/P R/P R/P R/P R/P R/P FPLLODIV<2:0> R/P R/P R/P R/P R/P FPLLMULT<6:0>
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-5: DEVCFG2/ADEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 3 Reserved: Write as ‘1’ bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = Divide by 8 110 = Divide by 7 101 = Divide by 6 100 = Divide by 5 011 = Divide by 4 010 = Divide by 3 001 = Divide by 2 000 = Divide by 1 DS60001320B-page 594 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-6: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3/ADEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 r-1 R/P R/P — FUSBIDIO IOL1WAY bit 29 bit 28 bit 27 bit 26 bit 25 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 R/P R/P PMDL1WAY PGL1WAY Bit 25/17/9/1 Bit 24/16/8/0 r-1 R/P R/P — FETHIO FMIIEN r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P R/P R/P R/P R/P R/P R/P
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-7: Bit Range 31:24 23:16 15:8 7:0 CFGCON: CONFIGURATION CONTROL REGISTER Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — DMAPRI(1) CPUPRI(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — ICACLK(1) OCACLK(1) U-0 U-0 R/W-0 U-0 U-0 R/W-0 — — USBSSEN(1) R/W-1 R/W-0
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-7: CFGCON: CONFIGURATION CONTROL REGISTER (CONTINUED) bit 7 IOANCPEN: I/O Analog Charge Pump Enable bit The analog IO charge pump improves analog performance when the device is operating at lower voltages. However, the charge pumps consume additional current.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-8: Bit Range 31:24 23:16 15:8 7:0 CFGEBIA: EXTERNAL BUS INTERFACE ADDRESS PIN CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 EBIPINEN — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EBIA23EN EBIA22EN EBIA21EN EBIA20EN EBIA19EN EBIA18EN EBIA17EN EBIA
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-9: Bit Range 31:24 23:16 15:8 7:0 CFGEBIC: EXTERNAL BUS INTERFACE CONTROL PIN CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 EBI RDYINV3 EBI RDYINV2 EBI RDYIN1 R/W-0 R/W-0 U-0 — EBI RDYEN3 EBI RDYEN2 EBI RDYEN1 — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 EBIRPEN — — — — — — E
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-9: bit 12 CFGEBIC: EXTERNAL BUS INTERFACE CONTROL PIN CONFIGURATION REGISTER (CONTINUED) EBIOEEN: EBIOE Pin Enable bit 1 = EBIOE pin is enabled for use by the EBI module 0 = EBIOE pin is available for general use bit 11-10 Unimplemented: Read as ‘0’ bit 9 EBIBSEN1: EBIBS1 Pin Enable bit 1 = EBIBS1 pin is enabled for use by the EBI module 0 = EBIBS1 pin is available for general use bit 8 EBIBSEN1: EBIBS0 Pin Enable bit 1 = E
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-10: CFGPG: PERMISSION GROUP CONFIGURATION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 FCPG<1:0> R/W-0 R/W-0 CAN2PG<1:0> U-0 U-0 — — Legend: R = Readable bit -n = Value at POR SQI1PG<1:0> R/W-0 R/W-0 CA
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 34-11: DEVID: DEVICE AND REVISION ID REGISTER Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R R R R R VER<3:0>(1) R 23:16 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R DEVID<27:24>(1) R R R R R R R (1) R R R R R R R DEVID<23:16>(1) 15:8 R R R R R R R DEVID<15:8> 7:0 R DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimple
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 34.3 FIGURE 34-1: On-Chip Voltage Regulator The core and digital logic for all PIC32MZ EF devices is designed to operate at a nominal 1.8V. To simplify system designs, devices in the PIC32MZ EF family incorporate an on-chip regulator providing the required core logic voltage from VDD. 34.3.1 ON-CHIP REGULATOR AND POR It takes a fixed delay for the on-chip regulator to generate an output.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 604 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 35.0 INSTRUCTION SET The PIC32MZ EF family instruction set complies with the MIPS32® Release 5 instruction set architecture. The PIC32MZ EF device family does not support the following features: • Core extend instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.imgtec.com for more information. 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 606 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 36.0 DEVELOPMENT SUPPORT 36.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 36.2 MPLAB XC Compilers 36.4 The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 36.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 36.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 36.12 Third-Party Development Tools A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 37.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MZ EF electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MZ EF devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 37.1 DC Characteristics TABLE 37-1: Characteristic DC5 DC5b Note 1: OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) (Note 1) Temp. Range (in °C) Max. Frequency PIC32MZ EF Devices 2.1V-3.6V -40°C to +85°C 200 MHz — 2.1V-3.6V -40°C to +125°C 180 MHz Planned Comment Overall functional device operation at VBORMIN < VDD < VDDMIN is guaranteed, but not characterized. All device Analog modules, such as ADC, etc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Conditions Operating Voltage DC10 VDD Supply Voltage (Note 1) 2.1 — 3.6 V — DC12 VDR RAM Data Retention Voltage (Note 2) 2.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. No. Typical(2) Maximum(5) Units Conditions Power-Down Current (IPD) (Note 1) DC40k 0.7 7 mA -40°C DC40l DC40n 1.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ.(1) Max. Units DI18 Input Low Voltage I/O Pins with PMP I/O Pins SDAx, SCLx VSS VSS VSS — — — 0.15 * VDD 0.2 * VDD 0.3 * VDD V V V DI19 SDAx, SCLx VSS — 0.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-10: DC CHARACTERISTICS: I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. DI60a IICL DI60b IICH DI60c Note 1: 2: 3: 4: 5: 6: Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typical(1) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Sym. Characteristic Max. Units Conditions(1) Min. Typ. — — 0.4 V IOL 10 mA, VDD = 3.3V — — 0.4 V IOL 15 mA, VDD = 3.3V — — 0.4 V IOL 20 mA, VDD = 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Sym. Characteristic Max. Units Conditions(1) Min. Typ. 2.4 — — V IOH -10 mA, VDD = 3.3V 2.4 — — V IOH -15 mA, VDD = 3.3V 2.4 — — V IOH -20 mA, VDD = 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Sym.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-12: DC CHARACTERISTICS: PROGRAM MEMORY(3) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Sym. No. D130a Characteristics Typ.(1) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-14: COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 3): 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol No. D300 D301 D303 D304 D305 Note 1: 2: 3: 4: Min. Typical Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 37.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MZ EF device AC characteristics and timing parameters.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-2: EXTERNAL CLOCK TIMING OS30 OS20 OS31 OSC1 OS31 OS30 TABLE 37-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-18: SYSTEM TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-20: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No. Characteristics Min. Typ. Max. Units Conditions -5 — +5 % 0°C TA +85°C -8 — +8 % -40°C TA +85°C Internal FRC Accuracy @ 8.00 MHz(1) F20 Note 1: FRC Frequency calibrated at +25°C and 3.3V.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 37-1 for load conditions. DS60001320B-page 628 DO31 DO32 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-23: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. DO31 Characteristics(2) Symbol TIOR Standard Operating Conditions: 2.1V to 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-23: I/O TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS Param. No. DO32 Characteristics(2) Symbol TIOF Standard Operating Conditions: 2.1V to 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 37-24: RESETS TIMING Standard Operating Conditions: 2.1V to 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-6: TIMER1-TIMER9 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 37-1 for load conditions. TABLE 37-25: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-26: TIMER2-TIMER9 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units Conditions TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 37-1 for load conditions. TABLE 37-28: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx MSb In LSb SP30 Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure 37-1 for load conditions. DS60001320B-page 636 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-30: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typ.(2) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOX LSb SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 37-1 for load conditions. DS60001320B-page 638 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-31: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typ.(2) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX Bit 14 - - - -1 MSb In SP40 LSb In SP41 Note: Refer to Figure 37-1 for load conditions. TABLE 37-32: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 37-1 for load conditions. TABLE 37-33: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-33: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-14: SQI SERIAL INPUT TIMING CHARACTERISTICS SQICS1 TSCKH TSCKL TCLK SQICLK TDIH TDIS MSB SQIDx FIGURE 37-15: LSB SQI SERIAL OUTPUT TIMING CHARACTERISTICS SQICS1 TCC SQICS2 TCES TCHH TSCKH TSCKL TCLK TCEH TCHS SQICLK TDOV SQIDx 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-34: SQI TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No. SQ10 Symbol FCLK Characteristic(1,3) Min. Typ.(2) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 Start Condition Stop Condition SDAx Note: Refer to Figure 37-1 for load conditions. FIGURE 37-17: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM33 IM25 SDAx In IM40 IM45 IM40 SDAx Out Note: Refer to Figure 37-1 for load conditions.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-35: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No. IM21 TR:SCL IM25 TSU:DAT IM26 THD:DAT IM30 TSU:STA IM31 THD:STA IM33 TSU:STO IM34 THD:STO IM40 TAA:SCL IM45 IM50 IM51 Note Characteristics Min.(1) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-18: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 37-1 for load conditions. FIGURE 37-19: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS33 IS25 SDAx In IS45 IS40 IS40 SDAx Out Note: Refer to Figure 37-1 for load conditions.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-36: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-20: CiTx Pin (output) CANx MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 37-37: CANx MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-38: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. Symbol No. Device Supply AD01 AVDD AD02 AVSS Reference Inputs AD05 VREFH AD06 VREFL AD07 VREF Characteristics Module VDD Supply Module VSS Supply Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ. Max. Greater of VDD – 0.3 or 2.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-39: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS (2) AC CHARACTERISTICS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristics Min. No. Typ.(1) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-40: ADC SAMPLE TIMES WITH CVD ENABLED AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ.(1) Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-41: TEMPERATURE SENSOR SPECIFICATIONS AC CHARACTERISTICS Param. Symbol No. Characteristics Standard Operating Conditions (see Note 1): 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typical Max. Units Conditions TS10 VTS Rate of Change — -5 — mV/ºC — TS11 TR Resolution -2 — +2 ºC — TS12 IVTEMP Voltage Range 0.2 — 1.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-21: PARALLEL SLAVE PORT TIMING PMCSx PS5 PMRD PS6 PMWR PS4 PS7 PMD PS1 PS3 PS2 TABLE 37-42: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-22: PARALLEL MASTER PORT READ TIMING DIAGRAM TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 PBCLK2 PM4 Address PMA PM6 PMD Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCSx TABLE 37-43: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-23: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 PBCLK2 Address PMA PM2 + PM3 Address<7:0> PMD Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCSx TABLE 37-44: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-45: USB OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No. Characteristics(1) USB313 VUSB3V3 USB Voltage Min. Typ. Max. Units Conditions 3.0 — 3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-46: ETHERNET MODULE SPECIFICATIONS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-26: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN VILMAX TX Clock VIHMIN ETXD<3:0>, ETEN, ETXERR FIGURE 37-27: VILMAX ET7 RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN RX Clock VILMAX VIHMIN ERXD<3:0>, ERXDV, ERXERR VILMAX (Setup) ET10 ET10 (Hold) 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-28: EBI PAGE READ TIMING tEBI-RC tEBI-PRC tEBI-PRC tEBI-PRC PBCLK8 tEBICO tEBICO ADDRESS EBIA tEBICO tEBICO EBIA<1:0> 00 tEBICO 01 tEBICO 10 tEBICO 11 tEBICO tEBICO tEBICO tEBICO EBICSx 00 EBIBSx tEBICO tEBICO EBIOE tEBIDH tEBIDS EBID<15:0> FIGURE 37-29: tEBIDH tEBIDS READ DATA tEBIDH tEBIDS READ DATA tEBIDH tEBIDS READ DATA READ DATA EBI WRITE TIMING tEBI-AS tEBI-WP tEBI-WR PBCLK8 tEBICO tE
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 37-47: EBI TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No. Characteristic Min. Typ. Max.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 37-30: EJTAG TIMING CHARACTERISTICS TTCKcyc TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TTRST*low TTDOout TTDOzstate TRST* Defined Undefined Trf TABLE 37-49: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.1V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. No.
AC AND DC CHARACTERISTICS GRAPHS Note: The graphs provided are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
VOH – 12x DRIVER PINS FIGURE 38-7: 1.250 VOH (V) Ͳ0.140 1.150 Ͳ0.120 1.050 0.950 Voltage (V) IOH (A) Ͳ0.100 Ͳ0.080 Ͳ0.060 Ͳ0.040 0.850 0.750 0 650 0.650 0.550 Absolute Maximum Ͳ0.020 0.450 0.350 Preliminary 0.000 0.00 0.50 FIGURE 38-6: 1.00 1.50 2.00 2.50 3.00 3.50 3.00 3.50 VOL – 12x DRIVER PINS VOL (V) 0.140 0.120 0.100 2015 Microchip Technology Inc. IOL (A) TYPICAL TEMPERATURE SENSOR VOLTAGE 0.080 0.060 0.040 Absolute Maximum 0.020 0.000 0.00 0.50 1.00 1.50 2.00 2.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 39.0 PACKAGING INFORMATION 39.1 Package Marking Information 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN MZ2048EFH 064-I/MR e3 0510017 Example 64-Lead TQFP (10x10x1 mm) MZ2048EFH 064-I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) Example MZ2048EFH 100-I/PF XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 39.1 Package Marking Information (Continued) 100-Lead TQFP (12x12x1 mm) Example MZ2048EFH 100-I/PT XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN e3 0510017 124-Lead VTLA (9x9x0.9 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN MZ2048EFH 124-I/TL e3 0510017 144-Lead TQFP (16x16x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN MZ2048EFH 144-I/PH e3 0510017 144-Lead LQFP (20x20x1.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 39.2 Note: Package Details For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001320B-page 668 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D NOTE 2 A B E1/2 E1 A E A SEE DETAIL 1 N 4X N/4 TIPS 0.20 C A-B D 1 3 2 4X NOTE 1 0.20 H A-B D TOP VIEW A2 A 0.05 C SEATING PLANE 0.08 C 64 X b 0.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family & ' ! "# $ % 3 % & % ! % 4 %% 255))) & &5 " ) 4 ' % 4 $ % % " % D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 6 % & 7 & % 8!&( $ 7 7 " 77 . .
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001320B-page 674 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family & ' " " ! "# $ % 3 % & % ! % 4 %% 255))) & &5 " ) 4 ' % 4 $ % % " % D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 A2 L1 6 % & 7 & % 8!&( $ 7 7 " 77 . .
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001320B-page 676 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320B-page 678 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001320B-page 680 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001320B-page 682 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 144-Lead Plastic Low Profile Quad Flatpack (PL) – 20x20x1.40 mm Body, with 2.00 mm Footprint [LQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 144-Lead Plastic Low Profile Quad Flatpack (PL) – 20x20x1.40 mm Body, with 2.00 mm Footprint [LQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001320B-page 684 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320B-page 686 Preliminary 2015 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family APPENDIX A: MIGRATING FROM PIC32MX5XX/6XX/7XX TO PIC32MZ EF This appendix provides an overview of considerations for migrating from PIC32MX5XX/6XX/7XX devices to the PIC32MZ EF family of devices. The code developed for PIC32MX5XX/6XX/7XX devices can be ported to PIC32MZ EF devices after making the appropriate changes outlined in the following sections. A.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE A-1: OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED) PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature PLL Configuration The FNOSC<2:0> and NOSC<2:0> bits select between POSC and FRC. Selection of which input clock (POSC or FRC) is now done through the FPLLICLK/PLLICLK bits.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE A-1: OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED) PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature Crystal/Oscillator Selection for USB Any frequency that can be divided down to 4 MHz using UPLLIDIV, including 4, 8, 12, 16, 20, 40, and 48 MHz. If the USB module is used, the Primary Oscillator is limited to either 12 MHz or 24 MHz. Which frequency is used is selected using the UPLLFSEL (DEVCFG2<30>) bit.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE A-1: OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED) PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature Fail-Safe Clock Monitor (FSCM) On PIC32MX devices, the internal FRC became the clock source On PIC32MZ EF devices, a separate internal Backup FRC on a failure of the clock source. (BFRC) becomes the clock source upon a failure at the clock source.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.2 Analog-to-Digital Converter (ADC) The PIC32MZ EF family of devices has a new Pipelined ADC module that replaces the 10-bit ADC module in PIC32MX5XX/6XX/7XX devices; therefore, the use of Bold type to show differences is not used in the following table. Note that not all register differences are described in this section; however, the key feature differences are listed in Table A-3.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE A-3: ADC DIFFERENCES (CONTINUED) PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature Output Format On PIC32MX devices, the output format was decided for all ADC On PIC32MZ EF devices, the FRACT bit determines whether channels based on the setting of the FORM<2:0> bits. fractional or integer format is used.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.3 CPU The CPU in the PIC32MZ EF family of devices has been changed to the MIPS32 M-Class MPU architecture. This CPU includes DSP ASE, internal data and instruction L1 caches, and a TLB-based MMU. TABLE A-4: Table A-4 summarizes some of the key differences (indicated by Bold type) in the internal CPU registers.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.4 Resets The PIC32MZ EF family of devices has updated the resets modules to incorporate the new handling of NMI resets from the WDT, DMT, and the FSCM. In addition, some bits have been moved, as summarized in Table A-5.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.6 DMA The DMA controller in PIC32MZ EF devices is similar to the DMA controller in PIC32MX5XX/6XX/7XX devices. New features include the extension of pattern matching to two by bytes and the addition of the optional Pattern Ignore mode. Table A-7 lists differences (indicated by Bold type) that will affect software migration.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.7 Interrupts and Exceptions In addition, the IFSx, IECx, and IPCx registers for old peripherals have shifted to different registers due to new peripherals. Please refer to Section 7.0 “CPU Exceptions and Interrupt Controller” to determine where the interrupts are now located. The key difference between Interrupt Controllers in PIC32MX5XX/6XX/7XX devices and PIC32MZ EF devices concerns vector spacing.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.8 Flash Programming The PIC32MZ EF family of devices incorporates a new Flash memory technology. Applications ported from PIC32MX5XX/6XX/7XX devices that take advantage of Run-time Self Programming will need to adjust the Flash programming steps to incorporate these changes. TABLE A-9: Table A-9 lists the differences (indicated by Bold type) that will affect software migration.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE A-9: FLASH PROGRAMMING DIFFERENCES (CONTINUED) PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature Flash Programming The op codes for programming the Flash memory have been changed to accommodate the new quad-word programming and dual-panel features. The row size has changed to 2 KB (512 IW) from 128 IW. The page size has changed to 16 KB (4K IW) from 4 KB (1K IW).
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.9 Other Peripherals and Features Table A-10 lists the differences (indicated by Bold type) that will affect software and hardware migration. Most of the remaining peripherals on PIC32MZ EF devices act identical to their counterparts on PIC32MX5XX/6XX/7XX devices. The main differences have to do with handling the increased peripheral bus clock speed and additional clock sources.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE A-10: PERIPHERAL DIFFERENCES (CONTINUED) PIC32MX5XX/6XX/7XX Feature PIC32MZ EF Feature Ethernet On PIC32MZ EF devices, the input clock divider for the Ethernet module has expanded options to accommodate the faster peripheral bus clock.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A.10 Package Differences In general, PIC32MZ EF devices are mostly pin compatible with PIC32MX5XX/6XX/7XX devices; however, some pins are not. In particular, the VDD and VSS pins have been added and moved to different pins. In addition, I/O functions that were on fixed pins now will largely be on remappable pins.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family APPENDIX B: MIGRATING FROM PIC32MZ EC TO PIC32MZ EF The PIC32MZ EF devices are similar to PIC32MZ EC devices, with many feature improvements and new capabilities. This appendix provides an overview of considerations for migrating from PIC32MZ EC devices to the PIC32MZ EF family of devices. The code developed for PIC32MZ EC devices can be ported to PIC32MZ EF devices after making the appropriate changes outlined in the following sections.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family B.2 Analog-to-Digital Converter (ADC) The PIC32MZ EC family features a Pipelined ADC module, while the PIC32MZ EF family of devices has an entirely new 12-bit High-Speed SAR ADC module. Nearly all registers in this new ADC module differ from the registers in PIC32MZ EC devices. Due to this difference, code will not port from PIC32MZ EC devices to PIC32MZ EF devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family B.3 CPU B.4 The CPU in PIC32MZ EC devices is the microAptiv™ MPU architecture. The CPU in the PIC32MZ EF devices is the Series 5 Warrior M-Class M5150 MPU architecture. Most PIC32MZ EF M-Class core features are identical to the microAptiv™ core in PIC32MZ EC devices. The main differences are that in PIC32MZ EF devices, a floating-point unit (FPU) is included for improved math performance, and PC Sampling for performance measurement.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family B.6 Resets On PIC32MZ EF devices, the Reset module adds eight bits to the NMICNT field to make the time-out period before device Reset longer, as described in Table B-5. TABLE B-5: RESETS DIFFERENCES PIC32MZ EC Feature PIC32MZ EF Feature Countdown to Reset During NMIs On PIC32MZ EC devices, the NMICNT<7:0> field is eight bits long, giving a maximum of 256 instructions before the device Reset. B.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family B.10 Serial Quad Interface (SQI) On PIC32MZ EF devices, the SQI module supports double-data-rate (DDR) memories. Refer to 20.0 “Serial Quad Interface (SQI)” and Section 46. “Serial Quad Interface (SQI)” (DS60001128) for information. B.11 PMP On PIC32MZ EF devices, the PMP features the ability to buffer reads and writes in both directions, and can read and write from different addresses. Refer to 23.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family APPENDIX C: REVISION HISTORY Revision A (January 2015) This is the initial released version of the document. Revision B (July 2015) The document status was updated from Advance Information to Preliminary. The revision includes the following major changes, which are referenced by their respective chapter in Table C-1. In addition, minor updates to text and formatting were incorporated throughout the document.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE C-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description 27.0 “Random Number Generator The TRNGMODE bit was added to the RNGCON register (see Register 27-2). (RNG)” 28.0 “12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)” The S&H Block Diagram was updated (see Figure 28-2). The registers, ADCTRG4 through ADCTRG8, were removed.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family INDEX Symbols CPU (’y’ = 0-8))...................................................................... 96, 98 *’y’ = 0-8))............................................................................ 97 A AC Characteristics ............................................................ 624 ADC Specifications ................................................... 650 Analog-to-Digital Conversion Requirements.............
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Interrupt Controller IRG, Vector and Bit Location .................................... 118 M Memory Maps Devices with 1024 KB Program Memory and 256 KB RAM .................................................................... 63 Devices with 1024 KB Program Memory and 512 KB RAM .................................................................... 64 Devices with 2048 KB Program Memory ....................
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family ADCCMPENx (ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 6))..................................... 462 ADCCMPx (ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 6))..................................... 463 ADCCMPxCON (ADC Digital Comparator ‘x’ Control Register (‘x’ = 1 through 6)) .............................. 471 ADCCON1 (ADC Control Register 1) ....................... 439 ADCCON2 (ADC Control Register 2) ....
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DMACON (DMA Controller Control).......................... 183 DMASTAT (DMA Status) .......................................... 184 DMSTAT (Deadman Timer Status) ........................... 299 DMTCLR (Deadman Timer Clear) ............................ 298 DMTCNT (Deadman Timer Count) ........................... 300 DMTCON (Deadman Timer Control)......................... 297 DMTPRECLR (Deadman Timer Preclear) ................
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REFOxTRIM (Reference Oscillator Trim (’x’ = 1-4)) . 166 RNMICON (Non-maskable Interrupt Control) ........... 113 RPnR (Peripheral Pin Select Output)........................ 283 RSWRST (Software Reset) ...................................... 112 RTCALRM (RTC ALARM Control)............................ 397 RTCCON (RTCC Control)......................................... 395 RTCDATE (Real-Time Clock Date Value) ................
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family W WWW Address.................................................................. 717 WWW, On-Line Support...................................................... 12 DS60001320B-page 716 Preliminary 2015 Microchip Technology Inc.
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MZ XXXX EF E XXX A T - I / PT - XXX Example: PIC32MZ2048EFH144-I/PT: Embedded Connectivity PIC32, MIPS32® M-Class MPU core, 2048 KB program memory, 144-pin, with Floating Point Unit, Industrial temperature, TQFP package.
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