Datasheet

© 2010 Microchip Technology Inc. DS61156D-page 69
PIC32MX5XX/6XX/7XX
TABLE 4-12: I2C2 REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
(1)
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
5400 I2C2CON
31:16
0000
15:0 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0000
5410 I2C2STAT
31:16
0000
15:0 ACKSTAT TRSTAT
BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
5420 I2C2ADD
31:16
0000
15:0
ADD<9:0> 0000
5430 I2C2MSK
31:16
0000
15:0
MSK<9:0> 0000
5440 I2C2BRG
31:16
0000
15:0
I2C2BRG<11:0> 0000
5450 I2C2TRN
31:16
0000
15:0
I2CT1DATA<7:0> 0000
5460 I2C2RCV
31:16
0000
15:0
I2CR1DATA<7:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.