Datasheet
© 2010 Microchip Technology Inc. DS61156D-page 35
PIC32MX5XX/6XX/7XX
TRD0 — 97 A3 O — Trace Data Bits 0-3.
TRD1 — 96 C3 O —
TRD2 — 95 C4 O —
TRD3 — 92 B5 O —
PGED1 16 25 K2 I/O ST Data I/O pin for Programming/Debugging
Communication Channel 1.
PGEC1 15 24 K1 I ST Clock input pin for Programming/Debugging
Communication Channel 1.
PGED2 18 27 J3 I/O ST Data I/O pin for Programming/Debugging
Communication Channel 2.
PGEC2 17 26 L1 I ST Clock input pin for Programming/Debugging
Communication Channel 2.
MCLR
7 13 F1 I/P ST Master Clear (Reset) input. This pin is an
active-low Reset to the device.
AVDD 19 30 J4 P P Positive supply for analog modules. This pin
must be connected at all times.
AV
SS 20 31 L3 P P Ground reference for analog modules.
VDD 10, 26, 38,
57
2, 16, 37,
46, 62, 86
A7, C2,
C9, E5,
K8, F8,
G5, H4, H6
P — Positive supply for peripheral logic and I/O
pins.
VCAP/
VDDCORE
56 85 B7 P — CPU logic filter capacitor connection.
VSS 9, 25, 41 15, 36, 45,
65, 75
A8, B10,
D4, D5,
E7, F5,
F10, G6,
G7, H3
P — Ground reference for logic and I/O pins. This
pin must be connected at all times.
VREF+ 16 29 K3 I Analog Analog voltage reference (high) input.
VREF- 15 28 L2 I Analog Analog voltage reference (low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.