Datasheet
PIC32MX5XX/6XX/7XX
DS61156D-page 236 © 2010 Microchip Technology Inc.
Parallel Master Port (PMP) ............................................... 139
PIC32MX Family USB Interface Diagram ......................... 122
Pinout I/O Descriptions (table) ............................................ 26
Power-on Reset (POR)
and On-Chip Voltage Regulator ................................ 164
Power-Saving Features..................................................... 153
CPU Halted Methods ................................................ 153
Operation .................................................................. 153
with CPU Running..................................................... 153
Prefetch Cache ................................................................. 117
Program Flash Memory
Wait State Characteristics......................................... 180
R
Real-Time Clock and Calendar (RTCC)............................ 141
Register Maps ............................................................. 51–105
Registers
DDPCON (Debug Data Port Control)........................ 166
DEVCFG0 (Device Configuration Word 0 ................. 155
DEVCFG1 (Device Configuration Word 1 ................. 157
DEVCFG2 (Device Configuration Word 2 ................. 159
DEVCFG3 (Device Configuration Word 3 ................. 161
DEVID (Device and Revision ID) .............................. 162
Resets ............................................................................... 109
Revision History ................................................................ 230
S
Serial Peripheral Interface (SPI) ....................................... 133
Software Simulator (MPLAB SIM)..................................... 171
Special Features ............................................................... 155
T
Timer1 Module .................................................................. 125
Timer2/3, Timer4/5 Modules ............................................. 127
Timing Diagrams
10-Bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 0, SSRC<2:0> = 000) ......................... 208
10-Bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> =
00001)............................................................... 209
CAN I/O..................................................................... 202
EJTAG ...................................................................... 214
External Clock........................................................... 182
I/O Characteristics .................................................... 185
I2Cx Bus Data (Master Mode) .................................. 196
I2Cx Bus Data (Slave Mode) .................................... 199
I2Cx Bus Start/Stop Bits (Master Mode) ................... 196
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 199
Input Capture (CAPx)................................................ 189
OCx/PWM ................................................................. 190
Output Compare (OCx)............................................. 190
Parallel Master Port Read......................................... 211
Parallel Master Port Write ......................................... 212
Parallel Slave Port .................................................... 210
SPIx Master Mode (CKE = 0).................................... 191
SPIx Master Mode (CKE = 1).................................... 192
SPIx Slave Mode (CKE = 0)...................................... 193
SPIx Slave Mode (CKE = 1)...................................... 194
Timer1, 2, 3, 4, 5 External Clock............................... 188
UART Reception ....................................................... 138
UART Transmission (8-Bit or 9-Bit Data) .................. 138
Timing Requirements
CLKO and I/O ........................................................... 185
Timing Specifications
CAN I/O Requirements ............................................. 202
I2Cx Bus Data Requirements (Master Mode) ........... 197
I2Cx Bus Data Requirements (Slave Mode)............. 200
Input Capture Requirements..................................... 189
Output Compare Requirements................................ 190
Simple OCx/PWM Mode Requirements ................... 190
SPIx Master Mode (CKE = 0) Requirements............ 191
SPIx Master Mode (CKE = 1) Requirements............ 192
SPIx Slave Mode (CKE = 1) Requirements.............. 194
SPIx Slave Mode Requirements (CKE = 0).............. 193
U
UART ................................................................................ 137
USB On-The-Go (OTG) .................................................... 121
V
VCAP/VDDCORE pin............................................................ 164
Voltage Reference Specifications..................................... 181
Voltage Regulator (On-Chip) ............................................ 164
W
Watchdog Timer (WDT).................................................... 163
WWW, On-Line Support ..................................................... 23