PIC32MX5XX/6XX/7XX Family Data Sheet High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers © 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC32MX5XX/6XX/7XX High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers High-Performance 32-bit RISC CPU: Peripheral Features (Continued): • MIPS32® M4K® 32-bit core with 5-stage pipeline • 80 MHz maximum frequency • 1.56 DMIPS/MHz (Dhrystone 2.
PIC32MX5XX/6XX/7XX TABLE 1: PIC32MX USB AND CAN – FEATURES Device Pins Program Memory (KB) Data Memory (KB) USB CAN Timers/Capture/Compare DMA Channels (Programmable/ Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) USB and CAN PIC32MX575F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX575F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX575F256L
PIC32MX5XX/6XX/7XX TABLE 2: PIC32MX USB AND ETHERNET – FEATURES Device Pins Program Memory (KB) Data Memory (KB) USB Ethernet Timers/Capture/Compare DMA Channels (Programmable/ Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) USB and Ethernet PIC32MX675F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX675F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT, MR PI
PIC32MX5XX/6XX/7XX TABLE 3: PIC32MX USB, ETHERNET AND CAN – FEATURES Pins Program Memory (KB) Data Memory (KB) USB Ethernet CAN Timers/Capture/Compare DMA Channels (Programmable/ Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators JTAG Trace Packages(4) PIC32MX775F256H 64 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F512H 64 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX795F512H 64 51
PIC32MX5XX/6XX/7XX Pin Diagrams 64-Pin QFN C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN ETXEN/PMD5/RE5 1 ETXD0/PMD6/RE6 2 ETXD1/PMD7/RE7 3 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 4 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 5 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 6 MCLR 7 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 8 VSS 9 VDD 10 AN5/C1IN+/VBUSON/CN7/RB5 11 AN4/C1IN-/CN6/RB4 12 AN3/C2IN+/CN5/RB3 13 AN2/C2IN-/CN4/RB2 14 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 SDA1A/SDI1A/U1ARX/OC3/RD2 EMDIO/AEMDIO/SCK1A/U1BTX/U1
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN ETXEN/PMD5/RE5 1 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 2 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 4 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 5 6 MCLR 7 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 8 VSS 9 VDD 10 AN5/C1IN+/VBUSON/CN7/RB5 11 AN4/C1IN-/CN6/RB4 12 AN3/C2IN+/CN5/RB3 13 AN2/C2IN-/CN4/RB2 14 Note: EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1 SDA1A/SDI1A/U1ARX/OC3/RD2 SCL1A/SDO1A/U1ATX/OC4/RD3 OC5/IC5/PMWR/CN13/RD4 PMRD/CN14/RD5 AETXEN/ETXERR/CN15/RD6 ETXCL
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1 SDA1A/SDI1A/U1ARX/OC3/RD2 SCL1A/SDO1A/U1ATX/OC4/RD3 OC5/IC5/PMWR/CN13/RD4 PMRD/CN14/RD5 AETXEN/ETXERR/CN15/RD6 ETXCLK/AERXERR/CN16/RD7 VCAP/VDDCORE VDD AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 ERXDV/ECRSDV/PMD2/RE2 ERXCLK/EREFCLK/PMD3/RE3 ERXERR/PMD4/RE4 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 1 ETXD0/PMD6/RE6 ETXD1/PMD7
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1 SDA1A/SDI1A/U1ARX/OC3/RD2 SCL1A/SDO1A/U1ATX/OC4/RD3 OC5/IC5/PMWR/CN13/RD4 PMRD/CN14/RD5 AETXEN/ETXERR/CN15/RD6 ETXCLK/AERXERR/CN16/RD7 VDD VCAP/VDDCORE C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 ERXD1/PMD0/RE0 ERXD0/PMD1/RE1 ERXDV/ECRSDV/PMD2/RE2 ERXCLK/EREFCLK/PMD3/RE3 ERXERR/PMD4/RE4 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 1 48 SOSCO/T1CK/C
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 C1TX/PMD10/RF1 C1RX/PMD11/RF0 VDD VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP RG15 1 75 VSS VDD 2 74 SOSCO/T1CK/CN0/RC14 PMD5/RE5 3 73 SO
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 C2RX/PMD8/RG0 C2TX/ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PMD7/RE7 T2CK/RC1 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3 T5CK/SDI1/RC4 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCAP/ VDDCORE RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC R
PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 SCL1/INT3/RA14 MCLR A5 PMD8/RG0 F1 A6 C1TX/PMD10/RF1 F2 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 A7 VDD F3 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 A8 VSS F4 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11
PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 AC1RX/SS3A/U3BRX/U3ACTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 K8 VDD L7 AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15 K9 SCK1A/U1BTX/U1ARTS/CN21/RD15 L8 K10 USBID/RF3 L9 SS1A/U1BRX/U1ACTS/CN20/RD14 K11 SDA1A/SDI1A/U1
PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 A2 PMD3/RE3 E9 AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL2A/SDO2A/ U2ATX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2A/U2BRX/ U2ACTS/PMA2/CN11/RG9 A8
PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 SS3A/U3BRX/U3ACTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 SCK3A/U3BTX/U3ARTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 K9 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 L8 K10 USBID/RF3 L9 AETXD0/SS1
PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 C2RX/PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/ U2ATX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/ U2ACTS/PMA2/CN11
PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 K5 No Connect (NC) L4 AVSS AN9/C2OUT/RB9 K6 AC1RX/SS3A/U3BRX/U3ACTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9
PIC32MX5XX/6XX/7XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 25 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 37 3.0 PIC32MX MCU................................................................................................
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 24 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Type Buffer Type K2 I Analog K1 I Analog 23 J2 I Analog 22 J1 I Analog 12 21 H2 I Analog 11 20 H1 I Analog AN6 17 26 L1 I Analog AN7 18 27 J3 I Analog AN8 21 32 K4 I Analog AN9 22 33 L4 I Analog AN10 23 34 L5 I Analog AN11 24 35 J5 I Analog Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA AN0 16 25 AN1 15 24 AN2 14 AN3 13 AN4 AN5 AN12 27 41 J7 I Analog
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B11 I ST 73 C10 I ST 25 K2 I ST 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I ST CN15 54 83 D7 I ST CN16 55 84 C7 I ST CN17 31 49 L10 I ST CN18
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA — 17 G3 RA0 Pin Type Buffer Type I/O ST RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST RA15 — 67 E8 I/O ST RB0 16 25 K2 I/O ST RB1 15 24 K1 I/
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name RD0 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA 46 72 D9 Pin Type Buffer Type I/O ST RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 —
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name Pin Type Buffer Type I/O ST Description 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA RG0 — 90 A5 RG1 — 89 E6 I/O ST RG6 4 10 E3 I/O ST RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST RG9 8 14 F3 I/O ST RG12 — 96 C3 I/O ST RG13 — 97 A3 I/O ST RG14 — 95 C4 I/O ST RG15 — 1 B2 I/O ST RG2 37 57 H10 I ST RG3 36 56 J11 I ST T1CK 48 74 B11 I ST T2CK — 6
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type D9 O — SPI1 data out. 69 E10 I/O ST SPI1 slave synchronization or frame pulse I/O. 49 48 K9 I/O ST Synchronous serial clock input/output for SPI1A. SDI1A 50 52 K11 I ST SPI1A data in. SDO1A 51 53 J10 O — SPI1A data out. SS1A 43 47 L9 I/O ST SPI1A slave synchronization or frame pulse I/O. SCK2A 4 10 E3 I/O ST Synchronous serial clock input/output for SPI2A.
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name Pin Type Buffer Type L2 I Analog Comparator Voltage Reference (low). K3 I Analog Comparator Voltage Reference (high). 34 L5 O Analog Comparator Voltage Reference output. 21 H2 I Analog Comparator 1 negative input.
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type A4 I/O TTL/ST 94 B4 I/O TTL/ST 98 B3 I/O TTL/ST 63 99 A2 I/O TTL/ST PMD4 64 100 A1 I/O TTL/ST PMD5 1 3 D3 I/O TTL/ST PMD6 2 4 C1 I/O TTL/ST Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA PMD0 60 93 PMD1 61 PMD2 62 PMD3 PMD7 3 5 D2 I/O TTL/ST PMD8 — 90 A5 I/O TTL/ST PMD9 — 89 E6 I/O TTL/ST Description Parallel Master Port data (Demultiple
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type L8 I ST Ethernet Receive Data 3.(2) 35 J5 I ST Ethernet receive error input.(2) 62 12 F2 I ST Ethernet receive data valid.(2) ECRSDV 61 12 F2 I ST Ethernet carrier sense data valid.(2) ERXCLK 63 14 F3 I ST Ethernet receive clock.(2) EREFCLK 63 14 F3 I ST Ethernet reference clock.(2) ETXD0 2 88 A6 O — Ethernet Transmit Data 0.
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type A3 O — 96 C3 O — 95 C4 O — — 92 B5 O — PGED1 16 25 K2 I/O ST Data I/O pin for Programming/Debugging Communication Channel 1. PGEC1 15 24 K1 I ST Clock input pin for Programming/Debugging Communication Channel 1. PGED2 18 27 J3 I/O ST Data I/O pin for Programming/Debugging Communication Channel 2.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 36 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.
PIC32MX5XX/6XX/7XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic CBP R1 MCLR C VDD VCAP/VDDCORE R VSS CEFC VDD PIC32MX VSS 10 Ω 2.2.1 VDD 0.1 µF Ceramic CBP VSS VDD AVSS VDD AVDD 0.1 µF Ceramic CBP VSS 0.1 µF Ceramic CBP 0.1 µF Ceramic CBP BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. 2.3 2.3.1 2.
PIC32MX5XX/6XX/7XX 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PIC32MX5XX/6XX/7XX 2.8 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them.
PIC32MX5XX/6XX/7XX PIC32MX MCU Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “MCU” (DS61113) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.mips.com.
PIC32MX5XX/6XX/7XX 3.2 Architecture Overview The PIC32MX5XX/6XX/7XX family core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller 3.2.
PIC32MX5XX/6XX/7XX TABLE 3-1: PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, MSUB/MSUBU 16 bits 1 1 32 bits 2 2 MUL 16 bits 2 1 32 bits 3 2 DIV/DIVU 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32 The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers.
PIC32MX5XX/6XX/7XX TABLE 3-2: Register Number 0-6 COPROCESSOR 0 REGISTERS Register Name Reserved Function Reserved in the PIC32MX5XX/6XX/7XX family core. 7 HWREna Enables access via the RDHWR instruction to selected hardware registers. 8 BadVAddr(1) Reports the address for the most recent address-related exception. 9 Count(1) Processor cycle count. 10 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core. 11 Compare(1) Timer interrupt control.
PIC32MX5XX/6XX/7XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS EJTAG debug single step. DINT EJTAG debug interrupt.
PIC32MX5XX/6XX/7XX 3.3 Power Management The PIC32MX5XX/6XX/7XX family core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction.
PIC32MX5XX/6XX/7XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. “Memory Organization” (DS61115) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space.
PIC32MX5XX/6XX/7XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0
PIC32MX5XX/6XX/7XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0000
PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 Reserved 0xA001FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02F
BMXCON(1) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — BMXCHEDMA — — — — — 20/4 19/3 18/2 17/1 16/0 All Resets Register Name 2000 BUS MATRIX REGISTER MAP Bit Range Virtual Address (BF88_#) © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) 1000 INTCON 1010 INTSTAT 1020 IPTMR 31/15 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 1040 IFS0 IFS1 1060 1070 IFS2 IEC0 IEC1 — © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name 10B0 IPC2 10C0 IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 1140 1150 23/7 22/6 21/5 31:16 — — — INT2IP<2:0> 15:0 — — — IC2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000 IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 31:16 — — — 0000 INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 15:0 — — 0000 — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 31:16 — 0000 — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0>
Virtual Address (BF88_#) 1000 INTCON 1010 INTSTAT 1020 IPTMR 31/15 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — IFS0 1040 IFS1 — IFS2 1060 IEC0 1070 IEC1 23/7 22/6 21/5 — — — — — — — — — SS0 0000 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — — — — — — — I2C1MIF I2C1SIF I2C1BIF U1ARXIF IEC2 1090 IPC0 © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 1110 1130 IPC10 1140 IPC11 1150 IPC12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 31:16 — — — — — — OC5IP<2:0> OC5IS<1:0> 0000 15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 31:16 — — — AD1IP<2:0> AD1IS<1
Virtual Address (BF88_#) 1000 INTCON 1010 INTSTAT 1020 IPTMR 31/15 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — IFS0 1040 IFS1 — IFS2 1060 IEC0 1070 IEC1 23/7 22/6 21/5 — — — — — — — — — SS0 0000 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — — — — 0000 — — — I2C1MIF I2C1SIF I2C1BIF U1ARXIF IEC2 1090 IPC0 © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 IPC10 1140 IPC11 1150 IPC12 30/14 29/13 28/12 31:16 — — — — 15:0 — — — IC5IP<2:0> IC5IS<1:0> 31:16 — — — AD1IP<2:0> AD1IS<1:0> 15:0 31:16 — — — — — 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000 — — — T5IP<2:0> T5IS<1:0> 0000 — — — CNIP<2:0> CNIS<1:0> 0000 U1AIP<2:0> U1AIS<1:0> SPI1AIP<2:0> SPI1AIS<1:0> I2C1AIP<2:0
Virtual Address (BF88_#) 1000 INTCON 1010 INTSTAT 1020 IPTMR 31/15 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — IFS0 1040 IFS1 — IFS2 1060 IEC0 1070 IEC1 23/7 22/6 21/5 — — — — — — — — — SS0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — — — — 0000 — — — I2C1MIF I2C1SIF I2C1BIF U1ARXIF IEC2 1090 IPC0 © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 IPC10 1140 IPC11 1150 IPC12 30/14 29/13 31:16 — — — SPI1IP<2:0> 15:0 — — — IC5IP<2:0> 31:16 — — — AD1IP<2:0> 15:0 31:16 — — — — 28/12 — 27/11 26/10 I2C1IP<2:0> — 25/9 24/8 23/7 22/6 21/5 SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000 IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 U1AIP<2:0> U1AIS<1:0> SPI1AIP<2:0>
Virtual Address (BF88_#) 1000 INTCON 1010 INTSTAT 1020 IPTMR 31/15 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — IFS0 1040 IFS1 — IFS2 1060 IEC0 1070 IEC1 23/7 22/6 21/5 — — — — — — — — — SS0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — — — — 0000 — — — I2C1MIF I2C1SIF I2C1BIF U1ARXIF IEC2 1090 IPC0 © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name 10E0 IPC5 10F0 IPC6 1100 IPC11 1150 — — — SPI1IP<2:0> 15:0 — — — IC5IP<2:0> 31:16 — — — AD1IP<2:0> IPC12 — — — — 28/12 — 27/11 26/10 I2C1IP<2:0> — 25/9 24/8 23/7 22/6 21/5 SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000 IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 U1AIP<2:0> U1AIS<1:0> SPI1AIP<2:0> SPI1AIS<1:0> I2C1AIP<2:0> I2C1AIS<1:0> CMP2IP<2:0> CMP2IS<1:0> 0000
Virtual Address (BF88_#) 1000 INTCON 1010 INTSTAT 1020 IPTMR 31/15 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 1040 — 1060 IEC0 1070 IEC1 — — — — — — — — — SS0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — — — — 0000 — — — I2C1MIF I2C1SIF I2C1BIF U1ARXIF IEC2 1090 IPC0 © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 IPC10 1140 IPC11 1150 IPC12 30/14 29/13 31:16 — — — SPI1IP<2:0> 15:0 — — — IC5IP<2:0> 31:16 — — — AD1IP<2:0> 15:0 31:16 — — — — — — 28/12 27/11 I2C1IP<2:0> 26/10 25/9 24/8 23/7 22/6 21/5 SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000 IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 U1AIP<2:0> U1AIS<1:0> SPI1AIP<2:0>
Virtual Address (BF80_#) 0600 T1CON 0610 TMR1 0620 TMR2 0820 TMR3 TMR4 TMR5 © 2010 Microchip Technology Inc.
Virtual Address (BF80_#) Register Name 2000 IC1CON(1) IC1BUF 2200 IC2CON(1) 2210 IC2BUF 2400 IC3CON(1) 2410 IC3BUF 2600 IC4CON(1) 2610 IC4BUF 2810 IC5BUF 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — — 31:16 — — — — — — — — — 15:0 ON FRZ SIDL — — — FEDGE C32 ICTMR 31:16 31:16 — — — — — — — — — 15:0 ON FRZ SIDL — — — FEDGE C32 ICTMR 31:16 18/2 — — — ICOV ICBNE 17/1 16/0 — — ICM<2:0> 31:16 — — — — — — — — —
Virtual Address (BF80_#) 3000 OC1CON 3010 OC1R 3020 OC1RS 3200 OC2CON 3210 OC2R 3220 OC2RS 3400 OC3CON 3410 OC3R 3420 OC3RS 3600 OC4CON 3610 OC4R 3620 OC4RS 3800 OC5CON 3810 OC5R © 2010 Microchip Technology Inc.
Virtual Address (BF80_#) 5000 I2C1ACON 5010 I2C1ASTAT 5020 I2C1AADD 5030 I2C1AMSK 5040 I2C1ABRG 5050 I2C1ATRN 5060 I2C1ARCV 5100 I2C2ACON 5120 I2C2AADD 5130 I2C2AMSK 5140 I2C2ABRG I2C2ATRN 5160 I2C2ARCV 5200 I2C3ACON 5210 I2C3ASTAT 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0000 31:16
Virtual Address (BF80_#) 5230 I2C3AMSK 5240 I2C3ABRG I2C3ATRN 5260 I2C3ARCV 5300 I2C1CON 5310 I2C1STAT 5320 I2C1ADD 5330 I2C1MSK 5340 I2C1BRG 5350 I2C1TRN 5360 I2C1RCV 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — 31:16 — — — — — — 15:0 — — — — — — 31:16 — — — — — — 15:0 — — — — 31:16 — — — — — — — — 15:0 — — — — — —
Virtual Address (BF80_#) I2C2 REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) 5400 I2C2CON 5410 I2C2STAT 5420 I2C2ADD 5430 I2C2MSK 5440 I2C2BRG 5450 I2C2TRN 5460 I2C2RCV 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN G
Virtual Address (BF80_#) U1ASTA(1) 6020 U1ATXREG 6030 U1ARXREG 6040 U1ABRG(1) 6200 U1BMODE 6210 (1) U1BSTA(1) 6220 U1BTXREG 6230 U1BRXREG 6240 U1BBRG(1) 6400 U2AMODE(1) 6410 U2ASTA(1) 6420 U2ATXREG 6430 U2ARXREG © 2010 Microchip Technology Inc.
Virtual Address (BF80_#) 6640 U2BBRG(1) 6800 U3AMODE(1) 6810 U3ASTA(1) 6820 U3ATXREG 6830 U3ARXREG 6840 U3ABRG(1) 6A00 U3BMODE(1) 6A20 U3BTXREG 6A30 U3BRXREG 6A40 U3BBRG (1) 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — 15:0 — — — — — — — — — — — — RX8 31:16 — — — — — — — — 31:16 — — — — — — — — 15:0 ON FRZ SIDL IREN RTSMD — 31:16 — — 15:0 UTXISEL<1:0> 31:16 — 15:0 20/4 19/3 18/2 17/1 16/0 — — — —
Virtual Address (BF80_#) 5800 SPI1ACON 5810 SPI1ASTAT 5820 SPI1ABUF 5830 SPI1ABRG 5A00 SPI2ACON 5A10 SPI2ASTAT 5A20 SPI2ABUF 5A30 SPI2ABRG 5C00 SPI3ACON 5C10 SPI3ASTAT 5C20 SPI3ABUF 5C30 SPI3ABRG 31/15 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL FRZ SIDL 31:16 — — — 15:0 — — — 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 24/8 23/7 — CKE SSEN — — — SRMT SPIROV SPIRBE FRMCNT<2:0> MODE16 SMP RXBUFELM<4:0> — SPIBUSY — — 31:16 SPITUR 22/6 21/5 20/4 19/3 18
Register Name 5E10 SPI1STAT SPI1BUF 5E30 SPI1BRG 31/15 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL FRZ SIDL 31:16 — — — 15:0 — — — 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 24/8 23/7 — CKE SSEN — — — SRMT SPIROV SPIRBE FRMCNT<2:0> MODE16 SMP RXBUFELM<4:0> — SPIBUSY — — 31:16 SPITUR 22/6 21/5 20/4 19/3 18/2 17/1 — — CKP MSTEN — — — SPIFE — STXISEL<1:0> 16/0 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> — SPITBE — 31:16 — — — — — —
Register Name 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL (1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 © 2010 Microchip Technology Inc.
ADC REGISTER MAP (CONTINUED) Register Name 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 ADC Result Word C (ADC1BUFC<31:0>) 21/5 20/4 19/3 18/2 17/1 All Resets Bits Bit Range Virtual Address (BF80_#) © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) DMASTAT 3020 DMAADDR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — 0000 31:16 — — — 15:0 ON FRZ SIDL 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — RDWR SUSPEND DMABUSY 31:16 DMACH<2:0> 0000 0000 DMAADDR<31:0> 15:0 0000 Legend: x = unknown value on Reset; — = unimplemented, r
Virtual Address (BF88_#) 3060 DCH0CON 3070 DCH0ECON 3080 DCH0INT 3090 DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30F0 DCH0CSIZ 3100 DCH0CPTR DCH0DAT 3120 DCH1CON 3130 DCH1ECON 3140 DCH1INT 3150 DCH1SSA DS61156D-page 77 3160 DCH1DSA 3170 DCH1SSIZ 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED 31:16 — — — — — — — — CFORCE CABORT PATEN SIRQEN AIRQEN — — — 31:16 — — — — — —
Virtual Address (BF88_#) 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 DCH2INT 3210 DCH2SSA 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) 32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3330 DCH3CSIZ 3340 DCH3CPTR DCH3DAT 3360 DCH4CON 3370 DCH4ECON 3380 DCH4INT 3390 DCH4SSA DS61156D-page 79 33A0 DCH4DSA 33B0 DCH4SSIZ 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED 31:16 — — — — — — — — CFORCE CABORT PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — —
Virtual Address (BF88_#) 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR DCH4DAT 3420 DCH5CON 3430 DCH5ECON 3440 DCH5INT 3450 DCH5SSA 3460 DCH5DSA 3470 DCH5SSIZ 3480 DCH5DSIZ 3490 DCH5SPTR © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) 34E0 DCH6CON 34F0 DCH6ECON 3500 DCH6INT 3510 DCH6SSA 3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3550 DCH6SPTR 3570 DCH6CSIZ 3580 DCH6CPTR DCH6DAT 35A0 DCH7CON 35B0 DCH7ECON 35C0 DCH7INT 35D0 DCH7SSA DS61156D-page 81 35E0 DCH7DSA 35F0 DCH7SSIZ 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED 31:16 — — — — — — — — CFORCE CABORT PATEN SIRQEN AIRQEN — — — 31:16 — — — — — —
Virtual Address (BF88_#) 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR DCH7DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — 15:0 31:16 — — — — — — — 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — 15:0 — 0000 0000 CHCP
Virtual Address (BF80_#) A000 CM1CON A010 CM2CON A060 CMSTAT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — 15:0 — FRZ SIDL — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — — EVPOL<1:0> — CREF — — — CCH<1:0> — — All Resets Bit Range Bits Register Name 0000 0000 — — — — — EVPOL<1:0
Virtual Address (BF80_#) FLASH CONTROLLER REGISTER MAP F400 NVMCON(1) F410 NVMKEY F420 NVMADDR(1) F430 NVMDATA F440 NVMSRC ADDR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — 31:16 — — — — — — — — — — — — 15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — 31:16 15:0 31:16 15:0 31:16 NVMOP<3:0> 31:16 NVMKEY<31:0> 0000 NVMADDR<31:0> 0000 0000 0000 0000 0000 0000 NVMSRCADDR<31:0> 15:0 0000 0000 NVMDAT
Virtual Address (BF88_#) Register Name 6000 TRISA 6010 PORTA 6020 LATA 6030 ODCA PORTA REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 All Resets Bits Bit Range 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRIS
Virtual Address (BF88_#) Register Name 6080 TRISC 6090 PORTC REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) PORTC 60A0 LATC 60B0 ODCC 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — —
Virtual Address (BF88_#) Register Name 60C0 TRISD 60D0 PORTD 60E0 LATD 60F0 ODCD PORTD REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 All Resets Bits Bit Range 31/15 30/14 29/13 28/12 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD
Virtual Address (BF88_#) Register Name 6100 TRISE PORTE REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) 6110 PORTE 6120 LATE 6130 ODCE 23/7 22/6 21/5 20/4 19/3 18/2 17/1 All Resets Bit Range Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4
Virtual Address (BF88_#) Register Name 6140 TRISF PORTF REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) 6150 PORTF 6160 LATF 6170 ODCF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — TRISF5 31:16 — — — — — — — — — — — 20/4 17/1 16/0 All Resets Bits Bit Range 19/3 18
Virtual Address (BF88_#) Register Name 6180 TRISG 61A0 LATG ODCG 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 31:16 — — — — — — — — 15:0 — — — — — — TRISG9 TRISG8 — — — — TRISG7 TRISG6 — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — RG9 RG8 RG7 RG6 — 31:16 — — — — — — — — — — 15:0 — — — — — — LATG9 LATG8 LATG7 31:16 — — — — — — — — 15:0 — — — — — — ODCG9 ODCG8 19/3 All Resets
Virtual Address (BF88_#) CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1) 61C0 CNCON 61D0 CNEN 61E0 CNPUE 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name 31:16 — — — — — — — — — — — — — — — — 15:0 ON FRZ SIDL — — — — — — — — — — — — —
Virtual Address (BF80_#) Register Name 7000 PMCON 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 PMDIN 7050 PMAEN 7060 PMSTAT 31/15 30/14 29/13 31:16 — — — 15:0 ON FRZ SIDL 31:16 — — — 15:0 BUSY 31:16 — IRQM<1:0> — — 28/12 27/11 — — ADRMUX<1:0> — — INCM<1:0> — — 26/10 25/9 24/8 23/7 22/6 — — — — — PMPTTL PTWREN PTRDEN — — — MODE16 — — MODE<1:0> — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — ALP CS2P CS1P — WRSP RDSP 0000 — — — — — —
Virtual Address (BF88_#) PREFETCH REGISTER MAP 4000 CHECON(1,2) 4010 CHEACC(1) 4020 CHETAG(1) 4030 CHEMSK 4040 (1) CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 CHELRU 4090 CHEHIT 40A0 CHEMIS 40C0 CHEPFABT 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — — — — — — — — — 15:0 — — — — — — — 31:16 CHEWEN — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — 31:16 LTAGBOOT 15:0 31:16 DCSZ<1:0> — 31:16 31:16 15:0 31:16 15:0 31
Virtual Address (BF80_#) Register Name 0200 RTCCON 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — 15:0 ON FRZ SIDL — — — — — — — — — 31:16 — — — — 15:0 ALRMEN CHIME PIV ALRMSYNC HR01<3:0> 15:0 SEC10<3:0> SEC01<3:0> 31:16 YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 HR10<3:0> HR01<3:0> 15:0 SEC10<3:0> — — — DAY10<3:0> — — 20/4 19/3
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY 2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 Legend: 31/15 30/14 31:16 FVBUSIO FUSBIDIO 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 FSCMIO — — FCANIO FETHIO FMIIEN — — — — — FSRSSEL<2:0> — — — — FPLLODIV<2:0> xxxx — FPLLIDIV<2:0> xxxx 15:0 18/2 17/1 16/0 xxxx USERID<15:0> 31:16 — — — — — 15:0 UPLLEN — — — — 31:16 — — — — — — 15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC 31:16 — — —
Virtual Address (BF88_#) Register Name 5040 U1OTGIR 5050 U1OTGIE 5070 U1OTGCON U1PWRC 5200 U1IR 5210 U1IE 5220 U1EIR 5230 5240 5250 © 2010 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name 52B0 U1SOF 52C0 52D0 52E0 U1BDTP2 U1BDTP3 U1CNFG1 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 U1EP4 5350 U1EP5 5360 U1EP6 5370 U1EP7 5380 U1EP8 5390 53B0 DS61156D-page 97 53C0 53D0 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13 Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — 31:16 — — — — — — —
Virtual Address (BF88_#) Register Name 53E0 U1EP14 53F0 U1EP15 USB REGISTER MAP (CONTINUED) Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 x = unknown value on Reset; — =
Virtual Address (BF88_#) Register Name B000 C1CON C1CFG B020 C1INT B030 B050 B060 C1VEC C1TREC C1FSTAT C1RXOVF B080 B090 B0A0 B0B0 C1TMR C1RXM0 C1RXM1 C1RXM2 C1RXM3 B0C0 C1FLTCON0 B0D0 C1FLTCON1 B0E0 C1FLTCON2 DS61156D-page 99 B0F0 C1FLTCON3 B100 C1FLTCON4 Legend: Note 1: 30/14 31:16 — 15:0 ON 31:16 — 15:0 SEG2PHTS 29/13 28/12 — — — ABAT — SIDLE — BUSY — — — — — — SAM 27/11 26/10 25/9 24/8 23/7 — — — — — — — — WAKFIL — — — REQOP<2:0> SEG1PH<2:0> 22/6
Virtual Address (BF88_#) B120 C1FLTCON6 B130 C1FLTCON7 B340 C1RXFn (n = 0-31) C1FIFOBA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 20/4 19/3 18/2 17/1 16/0 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000 31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000 15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000 31:16 FLTEN31 MSEL31<1:0> FS
Virtual Address (BF88_#) Register Name C000 C2CON C010 C2CFG C040 C050 C060 C080 C0A0 C0B0 C0B0 C2VEC C2TREC C2FSTAT C2RXOVF C2TMR C2RXM0 C2RXM1 C2RXM2 C2RXM3 C0C0 C2FLTCON0 C0D0 C2FLTCON1 DS61156D-page 101 C0E0 C2FLTCON2 C0F0 C2FLTCON3 Legend: Note 1: 30/14 31:16 — 15:0 ON 31:16 — 15:0 SEG2PHTS 29/13 28/12 — — — ABAT — SIDLE — BUSY — — — — — — SAM 27/11 26/10 25/9 24/8 23/7 — — — — — — — — WAKFIL — REQOP<2:0> SEG1PH<2:0> 22/6 21/5 OPMOD<2:0> PRSEG<2:
Virtual Address (BF88_#) C110 C2FLTCON5 C120 C2FLTCON6 C130 C2FLTCON7 C340 C2RXFn (n = 0-31) C2FIFOBA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 20/4 19/3 18/2 17/1 16/0 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000 31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000 15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000 31:16 FLTEN27
Virtual Address (BF88_#) Register Name 9000 ETHCON1 9010 ETHCON2 9020 9030 9040 9050 9060 9080 9090 ETHTXST ETHRXST ETHHT0 ETHHT1 ETHPMM0 ETHPMM1 ETHPMCS ETHPMO 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 15:0 ON FRZ SIDL — — — TXRTS RXEN 31:16 — — — — — — — — 15:0 — — — — — 31:16 90A0 ETHRXFC 90B0 ETHRXWM 90C0 ETHIEN 90D0 ETHIRQ DS61156D-page 103 Legend: Note 20/4 19/3 18/2 17/1 16/0 AUTOFC — — MANFC — — — — — — — — — — — 0000 — —
Virtual Address (BF88_#) Register Name 90E0 ETHSTAT ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — 15:0 — — — — — — — 9100 31:16 ETH RXOVFLOW 15:0 — — — — — — — 9110 31:16 ETH FRMTX
Virtual Address (BF88_#) Register Name 9260 EMACx SUPP ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — 15:0 — — — — — — — RESET RMII — 31:16 — — — — — 15:0 — — — — 31:16 — — — All Resets Bits Bit
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 106 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS61121) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 108 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS61118) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 110 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupt Controller” (DS61108) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority IPC0<1:0> Highest Natural Order Priority CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<2
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location IRQ Vector Number Flag Enable Priority Sub-Priority PMP – Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0> CMP1 – Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8> CMP2 – Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> U2AE – UART2A Error SPI2AE – SPI2A Fault I2C2AB – I2C2A Bus Collision Event 37 31 IFS1<5> IEC1<5> IPC7<28:2
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location IRQ Vector Number Flag Enable Priority Sub-Priority IC4E – Input Capture 5 Error 65 21 IFS2<1> IEC2<1> IPC5<12:10> IPC5<9:8> PMPE – Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1:0> U1BE – UART1B Error 67 49 IFS2<3> IEC2<3> IPC12<12:10> IPC12<9:8> U1BRX – UART1B Receiver 68 49 IFS2<4> IEC2<4> IPC12<12:10> IPC12<9:8> U1BTX – UART1B Transmitter 69 49
PIC32MX5XX/6XX/7XX 8.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 116 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX PREFETCH CACHE Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Prefetch Cache” (DS61119) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 118 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS61117) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 120 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 11.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS61126) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) Div x OSC1 PLL USB Suspend Div 2 UPLLEN(6) UPLLIDIV(6) OSC2 (PB Out)(1) UFRCEN(3) To Clock Generator for Core and Peripherals Sleep or Idle USB Module SRP Charge Bus UFIN(5) SRP Discharge USB Voltage Comparators 48 MHz USB Clock(7) Full Speed Pull-up D+(2) Registers and Control Interface Host Pull-dow
PIC32MX5XX/6XX/7XX 12.0 I/O PORTS General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.
PIC32MX5XX/6XX/7XX 12.1 Parallel I/O (PIO) Ports All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a Data Direction or Tri-State Control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset.
PIC32MX5XX/6XX/7XX 13.0 TIMER1 This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 126 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 14.0 TIMER2/3, TIMER4/5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
PIC32MX5XX/6XX/7XX FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1) Reset TMRy MS Half Word ADC Event Trigger(3) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx PRx 0 1 TGATE (TxCON<7>) Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’ in re
PIC32MX5XX/6XX/7XX 15.0 INPUT CAPTURE 2. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS61122) of the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 3. 4.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 130 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 16.0 OUTPUT COMPARE The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 132 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, A/D Converters, etc. The PIC32MX SPI module is compatible with Motorola® SPI and SIOP interfaces. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 134 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 18.0 INTER-INTEGRATED CIRCUIT (I2C™) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit” (DS61116) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS61156D-page 136 © 2010 Microchi
PIC32MX5XX/6XX/7XX 19.0 Note UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (DS61107) in the “PIC32MX (UART)” Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX Figure 19-2 and Figure 19-3 illustrate typical receive and transmit timing for the UART module.
PIC32MX5XX/6XX/7XX 20.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS61128) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 140 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) Following are some of the key features of this module: • • • • Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 142 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC Div 2 0 TAD ADCS<7:0> 1 8 TPB ADC Conversion Clock Multiplier 2, 4,..., 512 DS61156D-page 144 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 23.0 CONTROLLER AREA NETWORK (CAN) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. “Controller Area Network (CAN)” (DS61154) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 146 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 24.0 ETHERNET CONTROLLER Following are some of the key features of this module: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. “Ethernet Controller” (DS61155) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX Table 24-1, Table 24-2, Table 24-3 and Table 24-4 show four interfaces and the associated pins that can be used with the Ethernet Controller.
PIC32MX5XX/6XX/7XX 25.0 COMPARATOR Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. (DS61110) in the “Comparator” “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 150 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 26.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 152 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 27.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “Power-Saving Features” (DS61130) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX The processor will exit, or ‘wake-up’, from Sleep on one of the following events: The processor will wake or exit from Idle mode on the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset. • On a WDT time-out.
PIC32MX5XX/6XX/7XX 28.0 SPECIAL FEATURES Note: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the “PIC32MX Family Reference Manual” (DS61132), which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one’s compliment of the number of write-protected program Flash memory pages.
PIC32MX5XX/6XX/7XX REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — bit 31 bit 24 R/P r-1 r-1 FWDTEN — — R/P R/P R/P R/P R/P WDTPS<4:0> bit 23 bit 16 R/P R/P R/P FCKSM<1:0> R/P FPBDIV<1:0> r-1 R/P — OSCIOFNC R/P R/P POSCMOD<1:0> bit 15 bit 8 R/P r-1 R/P r-1 r-1 IESO — FSOSCEN — — R/P R/P R/P FNOSC<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Val
PIC32MX5XX/6XX/7XX REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4
PIC32MX5XX/6XX/7XX REGISTER 28-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 — — — — — R/P R/P R/P FPLLODIV<2:0> bit 23 bit 16 R/P r-1 r-1 r-1 r-1 UPLLEN — — — — R/P R/P R/P UPLLIDIV<2:0> bit 15 bit 8 r-1 R/P-1 — R/P R/P-1 r-1 FPLLMUL<2:0> R/P — R/P R/P FPLLIDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (
PIC32MX5XX/6XX/7XX REGISTER 28-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write ‘1’ bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider D
PIC32MX5XX/6XX/7XX REGISTER 28-4: DEVCFG3: DEVICE CONFIGURATION WORD 3 R/P R/P r-1 r-1 r-1 R/P R/P R/P FVBUSONIO FUSBIDIO — — — FCANIO FETHIO FMIIEN bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 — — — — — R/P R/P R/P FSRSSEL<2:0> bit 23 bit 16 R/P R/P R/P R/P R/P R/P R/P R/P USERID<15:8> bit 15 bit 8 R/P R/P R/P R/P R/P R/P R/P R/P USERID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unkno
PIC32MX5XX/6XX/7XX REGISTER 28-5: R DEVID: DEVICE AND REVISION ID REGISTER R R VER<3:0> R R (1) R R R (1) DEVID<27:24> bit 31 bit 24 R R R R R R R R DEVID<23:16>(1) bit 23 bit 16 R R R R R R R R DEVID<15:8>(1) bit 15 bit 8 R R R R R R R R DEVID<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID(1) Not
PIC32MX5XX/6XX/7XX 28.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-up Timer of the PIC32MX5XX/6XX/7XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode.
PIC32MX5XX/6XX/7XX 28.3 On-Chip Voltage Regulator 28.3.3 POWER-UP REQUIREMENTS All PIC32MX5XX/6XX/7XX devices’ core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX5XX/6XX/7XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. The on-chip regulator is designed to meet the power-up requirements for the device.
PIC32MX5XX/6XX/7XX 28.4 Programming and Diagnostics PIC32MX5XX/6XX/7XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them.
PIC32MX5XX/6XX/7XX REGISTER 28-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 — — — — — — — — bit 31 bit 24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 — — — — — — — — bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 — — — — — — — — bit 15 bit 8 r-0 r-0 r-0 r-0 R/W-1 R/W-0 r-0 R/W-0 — — — — JTAGEN TROEN — TDOEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1
PIC32MX5XX/6XX/7XX 29.0 INSTRUCTION SET The PIC32MX5XX/6XX/7XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features: • Core extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.mips.com for more information. © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX NOTES: DS61156D-page 168 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 30.
PIC32MX5XX/6XX/7XX 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
PIC32MX5XX/6XX/7XX 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC® MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC32MX5XX/6XX/7XX 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC32MX5XX/6XX/7XX 31.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC32MX5XX/6XX/7XX 31.1 DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Characteristic Temp. Range (in °C) PIC32MX5XX/6XX/7XX 2.3-3.6V -40°C to +85°C 80 MHz DC5 TABLE 31-2: Max. Frequency VDD Range (in Volts) THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max.
PIC32MX5XX/6XX/7XX TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(3) Max.
PIC32MX5XX/6XX/7XX TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core Off, Clock On Base Current (Note 1) for PIC32MX575/675/695/775 Family Devices DC30 4.5 6.
PIC32MX5XX/6XX/7XX TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Units Conditions Power-Down Current (IPD) (Note 1) for PIC32MX575/675/695/775 Family Devices DC40 10 40 μA -40°C DC40a 36 100 μA +25°C 2.3V Base Power-Down Current (Note 6) DC40b 400 720 μA +85°C DC40c 41 120 μA +25°C 3.
PIC32MX5XX/6XX/7XX TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. VIL DI10 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min. Typical(1) Max. Units with TTL Buffer VSS — 0.15 VDD V (Note 4) with Schmitt Trigger Buffer VSS — 0.2 VDD V (Note 4) Characteristics Conditions Input Low Voltage I/O Pins: (2) DI15 MCLR VSS — 0.
PIC32MX5XX/6XX/7XX TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. VOL DO10 Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min. Typical Max. Units — — 0.4 V IOL = 7 mA, VDD = 3.6V — — 0.4 V IOL = 6 mA, VDD = 2.3V — — 0.4 V IOL = 3.5 mA, VDD = 3.6V — — 0.4 V IOL = 2.5 mA, VDD = 2.3V 2.4 — — V IOH = -12 mA, VDD = 3.6V 1.
PIC32MX5XX/6XX/7XX TABLE 31-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Required Flash Wait States SYSCLK Units Comments 0 Wait State 0 to 30 MHz — 1 Wait State 31 to 60 2 Wait States 61 to 80 TABLE 31-12: COMPARATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-13: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param. No. Symbol Characteristics Min. Typical Max. Units Comments VDD/24 — VDD/32 LSb — — — 1/2 LSb — D310 VRES Resolution D311 VRAA Absolute Accuracy D312 TSET Settling Time(1) — — 10 μs — D313 VIREF Internal Voltage Reference — 0.
PIC32MX5XX/6XX/7XX 31.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX5XX/6XX/7XX AC characteristics and timing parameters. TABLE 31-15: AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Operating voltage VDD range.
PIC32MX5XX/6XX/7XX TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. OS10 FOSC OS11 Min. Typical(1) Max.
PIC32MX5XX/6XX/7XX TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max.
PIC32MX5XX/6XX/7XX FIGURE 31-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 31-1 for load conditions. DO31 DO32 TABLE 31-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(2) Min. Typical(1) Max. Units 5 15 ns VDD < 2.5V Conditions DO31 TIOR Port Output Rise Time — — 5 10 ns VDD > 2.
PIC32MX5XX/6XX/7XX FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) SY10 (TOST) CPU Starts Fetching Code External VDDCORE Provided Clock Sources
PIC32MX5XX/6XX/7XX FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 31-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 31-1 for load conditions. TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. TA10 TA11 TA15 Symbol TTXH TTXL TTXP Characteristics(2) TxCK High Time TxCK Low Time Typical Max.
PIC32MX5XX/6XX/7XX TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. Characteristics(1) Symbol Min. Max. Units Conditions TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns — ns TB11 TTXL TxCK Low Time Synchronous, with prescaler [(12.
PIC32MX5XX/6XX/7XX FIGURE 31-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 31-1 for load conditions. TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max.
PIC32MX5XX/6XX/7XX FIGURE 31-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx MSb In LSb SP30 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max.
PIC32MX5XX/6XX/7XX FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 31-1 for load conditions. DS61156D-page 196 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. IM10 IM11 IM20 Min.(1) Max.
PIC32MX5XX/6XX/7XX TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. IM40 IM45 IM50 Note 1: 2: TAA:SCL Output Valid From Clock TBF:SDA Bus Free Time CB Min.(1) Max. Units Conditions 100 kHz mode — 3500 ns — 400 kHz mode — 1000 ns — 1 MHz mode (Note 2) — 350 ns — 100 kHz mode 4.
PIC32MX5XX/6XX/7XX FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 31-1 for load conditions. © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. IS10 IS11 IS20 IS21 Symbol TLO:SCL THI:SCL TF:SCL TR:SCL Characteristics Clock Low Time Clock High Time SDAx and SCLx Fall Time SDAx and SCLx Rise Time Min. Max. Units 100 kHz mode 4.7 — μs PBCLK must operate at a minimum of 800 kHz 400 kHz mode 1.
PIC32MX5XX/6XX/7XX TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. IS34 IS40 Symbol THD:STO TAA:SCL Characteristics Stop Condition Hold Time Min. Max.
PIC32MX5XX/6XX/7XX FIGURE 31-18: CiTx Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
PIC32MX5XX/6XX/7XX TABLE 31-35: ETHERNET MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Characteristic Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min. Typical Max. Units Conditions Device Supply ET20a Module VDD Supply 2.5 — 3.6 V ET20b Module VDD Supply 2.7 — 3.
PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min. Typical Max. Units Conditions Greater of VDD – 0.3 or 2.5 — Lesser of VDD + 0.3 or 3.6 V VSS — VSS + 0.
PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min. Typical Max. Units Conditions ADC Accuracy – Measurements with Internal VREF+/VREF- AD20d Nr Resolution AD21d INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-37: 10-BIT CONVERSION RATE PARAMETERS PIC32MX 10-bit A/D Converter Conversion Rates(2) ADC Speed 1 Msps to 400 ksps(1) Sampling TAD RS Max Minimum Time Min 65 ns 132 ns 500Ω VDD Temperature 3.0V to 3.6V -40°C to +85°C ADC Channels Configuration VREF- VREF+ CHX ANx Up to 400 ksps 200 ns 200 ns 5.0 kΩ 2.5V to 3.6V SHA ADC -40°C to +85°C VREF- VREF+ or or AVSS AVDD CHX ANx SHA ADC ANx or VREF- Up to 300 ksps 200 ns 200 ns 5.0 kΩ 2.5V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-38: A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max. Units A/D Clock Period(2) 65 — — ns Characteristics Conditions Clock Parameters AD50 TAD See Table 31-37 Conversion Rate AD55 TCONV Conversion Time — 12 TAD — — AD56 FCNV Throughput Rate (Sampling Speed) — — 1000 ksps AVDD = 3.
PIC32MX5XX/6XX/7XX FIGURE 31-19: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in the “PIC32MX Family Reference Manual” (DS61132).
PIC32MX5XX/6XX/7XX FIGURE 31-20: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period.
PIC32MX5XX/6XX/7XX FIGURE 31-21: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical Max.
PIC32MX5XX/6XX/7XX FIGURE 31-22: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min.
PIC32MX5XX/6XX/7XX FIGURE 31-23: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max.
PIC32MX5XX/6XX/7XX TABLE 31-42: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) USB313 VUSB USB Voltage Min. Typical Max. Units 3.0 — 3.6 V Conditions Voltage on bus must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V USB316 VIHUSB Input High Voltage for USB Buffer 2.
PIC32MX5XX/6XX/7XX FIGURE 31-24: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Trf Undefined TABLE 31-43: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max.
PIC32MX5XX/6XX/7XX 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX575F 512H-80I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC32MX5XX/6XX/7XX 32.1 Package Marking Information (Continued) 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 121-Lead XBGA (10x10x1.1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS61156D-page 216 Example PIC32MX575F 512H-80I/MR e3 0510017 Example PIC32MX575F 512H-80I/BG e3 0510017 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 32.2 Package Details The following sections give the technical details of the packages.
PIC32MX5XX/6XX/7XX ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 DS61156D-page 218 # * !( 4 ! ! & 4 % & & # & © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 8 89 : / 1 + = = / / / = / 3 & 7 & 7 / ; / 3 & & 7 # # 4 4 !
PIC32MX5XX/6XX/7XX ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 DS61156D-page 220 # * !( 4 ! ! & 4 % & & # & © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 77 . .
PIC32MX5XX/6XX/7XX ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 DS61156D-page 222 # * !( 4 ! ! & 4 % & & # & © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156D-page 224 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156D-page 226 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156D-page 228 © 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below. A.1 DMA PIC32MX5XX/6XX/7XX devices do stopping DMA transfers in Idle mode. A.2 not A.
PIC32MX5XX/6XX/7XX APPENDIX B: REVISION HISTORY Revision B (November 2009) The revision includes the following global update: Revision A (August 2009) This is the initial released version of this document. • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. Other major changes are referenced by their respective chapter/section in Table B-1.
PIC32MX5XX/6XX/7XX TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 4.0 “Memory Organization” Update Description Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-1 to include the PIC32MX575F256L device. Updated the title of Figure 4-3 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device.
PIC32MX5XX/6XX/7XX Revision C (February 2010) The revision includes the following updates, as described in Table B-2: TABLE B-2: MAJOR SECTION UPDATES Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Update Description Added the following devices: • • • • • • PIC32MX675F256H PIC32MX775F256H PIC32MX775F512H PIC32MX675F256L PIC32MX775F256L PIC32MX775F512L Added the following pins: • • • • EREFCLK ECRSDV AEREFCLK AECRSDV Added the EREFCLK and ECRSDV pins to Table 5
PIC32MX5XX/6XX/7XX TABLE B-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 4.0 “Memory Organization” Update Description Added new devices and updated the virtual and physical memory map values in Figure 4-1. Added new devices to Figure 4-2.
PIC32MX5XX/6XX/7XX Revision D (June 2010) The revision includes the following updates, as described in Table B-3: TABLE B-3: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Updated the initial Flash memory range to 64K. Section 4.0 “Memory Organization” Added new Memory Maps (Figure 4-1, Figure 4-2 and Figure 4-3). Updated the initial SRAM memory range to 16K.
PIC32MX5XX/6XX/7XX INDEX Numerics D 10-Bit Analog-to-Digital Converter (ADC) ......................... 143 DC Characteristics............................................................ 174 I/O Pin Input Specifications ...................................... 178 I/O Pin Output Specifications.................................... 179 Idle Current (IIDLE) .................................................... 176 Operating Current (IDD) ............................................ 175 Power-Down Current (IPD)..
PIC32MX5XX/6XX/7XX Parallel Master Port (PMP) ............................................... 139 PIC32MX Family USB Interface Diagram ......................... 122 Pinout I/O Descriptions (table) ............................................ 26 Power-on Reset (POR) and On-Chip Voltage Regulator ................................ 164 Power-Saving Features..................................................... 153 CPU Halted Methods ................................................ 153 Operation ..................
PIC32MX5XX/6XX/7XX Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Example: PIC32MX575F256H-80I/PT: General purpose PIC32MX, 256 KB program memory, 64-pin, Industrial temperature, TQFP package.
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