PIC32MX5XX/6XX/7XX 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Graphics Interface, USB, CAN, and Ethernet Operating Conditions Timers/Output Compare/Input Capture • 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 1: PIC32MX5XX USB AND CAN FEATURES Program Memory (KB) Data Memory (KB) USB CAN Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2C(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) PIC32MX534F064H 64 64 + 12(1) 16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F128H 64 128 + 12(1) 32 1 1 5/5
PIC32MX5XX/6XX/7XX TABLE 2: PIC32MX6XX USB AND ETHERNET FEATURES Program Memory (KB) Data Memory (KB) USB Ethernet Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2C(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) PIC32MX664F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX664F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX675F256H 64 256 + 12(1) 64
PIC32MX5XX/6XX/7XX TABLE 3: PIC32MX7XX USB, ETHERNET, AND CAN FEATURES Pins Program Memory (KB) Data Memory (KB) USB Ethernet CAN Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2C(3) 10-bit 1 Msps ADC (Channels) Comparators JTAG Trace Packages(4) PIC32MX764F128H 64 128 + 12(1) 32 1 1 1 5/5/5 4/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F256H 64 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F512H 64 51
PIC32MX5XX/6XX/7XX Device Pin Tables TABLE 4: PIN NAMES FOR 64-PIN USB AND CAN DEVICES 64-PIN QFN(2) AND TQFP (TOP VIEW) PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX575F256H PIC32MX575F512H 64 1 QFN(2) 64 1 TQFP Pin # Full Pin Name Pin # Full Pin Name 1 PMD5/RE5 33 USBID/RF3 2 PMD6/RE6 34 VBUS 3 PMD7/RE7 35 VUSB3V3 4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3 5 SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2 6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 VDD 7 MCLR 39 OSC1/CLKI/RC12
PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES FOR 64-PIN USB AND ETHERNET DEVICES 64-PIN QFN(2) AND TQFP (TOP VIEW) PIC32MX664F064H PIC32MX664F128H PIC32MX675F256H PIC32MX675F512H PIC32MX695F512H 64 1 QFN(2) 64 1 TQFP Pin # Full Pin Name Pin # Full Pin Name 1 ETXEN/PMD5/RE5 33 USBID/RF3 2 ETXD0/PMD6/RE6 34 VBUS 3 ETXD1/PMD7/RE7 35 VUSB3V3 4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3 5 SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2 6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 VDD 7 MCLR 39 OSC1/CLKI/RC
PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES FOR 64-PIN USB, ETHERNET, AND CAN DEVICES 64-PIN QFN(3) AND TQFP (TOP VIEW) PIC32MX764F128H PIC32MX775F256H PIC32MX775F512H PIC32MX795F512H 64 1 QFN(3) 64 1 TQFP Pin # Full Pin Name 1 ETXEN/PMD5/RE5 2 3 4 Pin # Full Pin Name 33 USBID/RF3 ETXD0/PMD6/RE6 34 VBUS ETXD1/PMD7/RE7 35 VUSB3V3 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3 5 SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2 6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 VDD 7 MCLR 39 OSC1/CLKI/RC12 8 SS2/U
PIC32MX5XX/6XX/7XX TABLE 7: PIN NAMES FOR 100-PIN USB AND CAN DEVICES 100-PIN TQFP (TOP VIEW) PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F512L PIC32MX575F256L 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 RG15 36 VSS 2 VDD 37 VDD 3 PMD5/RE5 38 TCK/RA1 4 PMD6/RE6 39 AC1TX/SCK4/U5TX/U2RTS/RF13 5 PMD7/RE7 40 AC1RX/SS4/U5RX/U2CTS/RF12 6 T2CK/RC1 41 AN12/PMA11/RB12 7 T3CK/RC2 42 AN13/PMA10/RB13 8 T4CK/RC3 43 AN14/PMALH/PMA1/RB14 9 T5CK/SDI1/RC4 44 AN15/O
PIC32MX5XX/6XX/7XX TABLE 7: PIN NAMES FOR 100-PIN USB AND CAN DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW) PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F512L PIC32MX575F256L 100 1 Pin # Full Pin Name Pin # Full Pin Name 71 IC4/PMCS1/PMA14/RD11 86 VDD 72 SDO1/OC1/INT0/RD0 87 C1RX/PMD11/RF0 73 SOSCI/CN1/RC13 88 C1TX/PMD10/RF1 74 SOSCO/T1CK/CN0/RC14 89 PMD9/RG1 75 VSS 90 PMD8/RG0 76 OC2/RD1 91 TRCLK/RA6 77 OC3/RD2 92 TRD3/RA7 78 OC4/RD3 93 PMD0/RE0 79 IC5/PMD
PIC32MX5XX/6XX/7XX TABLE 8: PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES 100-PIN TQFP (TOP VIEW) PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 AERXERR/RG15 36 VSS 2 VDD 37 VDD 3 PMD5/RE5 38 TCK/RA1 4 PMD6/RE6 39 SCK4/U5TX/U2RTS/RF13 5 PMD7/RE7 40 SS4/U5RX/U2CTS/RF12 6 T2CK/RC1 41 AN12/ERXD0/AECRS/PMA11/RB12 7 T3CK/RC2 42 AN13/ERXD1/AECOL/PMA10/RB13 8 T4CK/RC3 43 AN14/ERXD2/AETXD3/PMALH/
PIC32MX5XX/6XX/7XX TABLE 8: PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW) PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 71 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 86 VDD 72 SDO1/OC1/INT0/RD0 87 ETXD1/PMD11/RF0 73 SOSCI/CN1/RC13 88 ETXD0/PMD10/RF1 74 SOSCO/T1CK/CN0/RC14 89 ETXERR/PMD9/RG1 75 VSS 90 PMD8/RG0 76 OC2/RD1 91 TRCLK/RA6 77 OC3/RD2 92 TRD3/RA7 78 OC4/RD3
PIC32MX5XX/6XX/7XX TABLE 9: PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES 100-PIN TQFP (TOP VIEW) PIC32MX764F128L PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 AERXERR/RG15 36 VSS 2 VDD 37 VDD 3 PMD5/RE5 38 TCK/RA1 4 PMD6/RE6 39 AC1TX/SCK4/U5TX/U2RTS/RF13 5 PMD7/RE7 40 AC1RX/SS4/U5RX/U2CTS/RF12 6 T2CK/RC1 41 AN12/ERXD0/AECRS/PMA11/RB12 7 T3CK/AC2TX(1)/RC2 42 AN13/ERXD1/AECOL/PMA10/RB13 8 T4CK/AC2RX(1)/RC3 43 AN14
PIC32MX5XX/6XX/7XX TABLE 9: PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW) PIC32MX764F128L PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L 100 1 Pin # 71 72 Full Pin Name Pin # Full Pin Name EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 SDO1/OC1/INT0/RD0 86 87 73 SOSCI/CN1/RC13 88 C1TX/ETXD0/PMD10/RF1 74 89 75 SOSCO/T1CK/CN0/RC14 VSS 90 C2TX(1)/ETXERR/PMD9/RG1 C2RX(1)/PMD8/RG0 76 OC2/RD1 91 TRCLK/RA6 77 OC3/RD2 92 TRD3/RA7 78 OC4/RD3 93 PMD0/RE0 79
PIC32MX5XX/6XX/7XX TABLE 10: PIN NAMES FOR USB AND CAN DEVICES 121-PIN TFBGA (BOTTOM VIEW) PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F256L PIC32MX575F512L Note: L11 L1 A11 The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX TABLE 10: PIN NAMES (CONTINUED)FOR USB AND CAN DEVICES 121-PIN TFBGA (BOTTOM VIEW) PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F256L PIC32MX575F512L Note: L11 L1 A11 The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX TABLE 11: PIN NAMES FOR USB AND ETHERNET DEVICES 121-PIN TFBGA (BOTTOM VIEW) L11 PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L Note: L1 A11 The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX TABLE 11: PIN NAMES FOR USB AND ETHERNET DEVICES (CONTINUED) 121-PIN TFBGA (BOTTOM VIEW) L11 PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L Note: L1 A11 The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX TABLE 12: PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES 121-PIN TFBGA (BOTTOM VIEW) L11 L1 PIC32MX764F128L PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L Note: A11 The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX TABLE 12: PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES (CONTINUED) 121-PIN TFBGA (BOTTOM VIEW) L11 L1 PIC32MX764F128L PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L Note: A11 The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX TABLE 13: PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES 124-PIN VTLA (BOTTOM VIEW)(2,3) A34 A17 B13 PIC32MX675F512L PIC32MX695F512L PIC32MX795F512L B29 Conductive Thermal Pad B41 B1 B56 A51 A1 Polarity Indicator Package Bump # Full Pin Name A68 Package Bump # Full Pin Name A1 No Connect (NC) A38 A2 AERXERR/RG15 A39 SCL2/RA2 A3 VSS A40 TDI/RA4 A4 PMD6/RE6 A41 VDD A5 T2CK/RC1 A42 OSC2/CLKO/RC15 A6 T4CK/AC2RX(1)/RC3 A43 VSS A7 ECOL/SCK2/U6TX/U3RTS/
PIC32MX5XX/6XX/7XX TABLE 13: PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED) 124-PIN VTLA (BOTTOM VIEW)(2,3) A34 A17 B13 PIC32MX675F512L PIC32MX695F512L PIC32MX795F512L B29 Conductive Thermal Pad B41 B1 B56 A51 A1 Polarity Indicator Package Bump # Full Pin Name A68 Package Bump # Full Pin Name B8 VSS B33 TDO/RA5 B9 TMS/RA0 B34 OSC1/CLKI/RC12 B10 AERXD1/INT2/RE9 B35 No Connect (NC) B11 AN4/C1IN-/CN6/RB4 B36 AETXCLK/SCL1/INT3/RA14 B12 VSS B37 RTCC/EMDIO/AEMDIO/
PIC32MX5XX/6XX/7XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 25 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 37 3.0 CPU ....................................................................................................
PIC32MX5XX/6XX/7XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC32MX5XX/6XX/7XX Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the PIC32MX795F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list.
PIC32MX5XX/6XX/7XX 1.0 Note: DEVICE OVERVIEW This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the documents listed in the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Name Pin Type Buffer Type Description 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA AN0 16 25 K2 B14 I Analog Analog input channels AN1 AN2 15 14 24 23 K1 J2 A15 B13 I I Analog Analog AN3 AN4 13 12 22 21 J1 H2 A13 B11 I I Analog Analog AN5 AN6 11 17 20 26 H1 L1 A12 A20 I I Analog Analog AN7 AN8 18 21 27 32 J3 K4 B16 A23 I I Analog Analog AN9 AN10 22 23 33 34 L4 L5 B19 A24 I I
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B40 I ST C10 K2 A47 B14 I I ST ST 24 23 K1 J2 A15 B13 I I ST ST 13 12 22 21 J1 H2 A13 B11 I I ST ST CN7 CN8 11 4 20 10 H1 E3 A12 A7 I I ST ST CN9 CN10 5 6 11 12 F4 F2 B6 A8 I I ST ST CN11 CN12 8 30 14 44 F3 L8 A9 A29 I I ST ST CN13 CN14 52 53 81 82 C8 B8 B44 A55 I I ST ST CN15 CN16 54 55 83 84 D7 C7 B45 A56 I I ST ST CN17 CN18 31 32 49 50 L10 L11 B2
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B9 I/O ST J6 H11 A26 A39 I/O I/O ST ST 59 60 G10 G11 B32 A40 I/O I/O ST ST — — 61 91 G9 C5 B33 B51 I/O I/O ST ST RA7 RA9 — — 92 28 B5 L2 A62 A21 I/O I/O ST ST RA10 RA14 — — 29 66 K3 E11 B17 B36 I/O I/O ST ST RA15 RB0 — 16 67 25 E8 K2 A44 B14 I/O I/O ST ST RB1 RB2 15 14 24 23 K1 J2 A15 B13 I/O I/O ST ST RB3 RB4 13 12 22 21 J1 H2 A13 B11 I/O I/O ST ST RB5
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B39 I/O ST A11 A10 A52 B42 I/O I/O ST ST 78 81 B9 C8 A53 B44 I/O I/O ST ST 53 54 82 83 B8 D7 A55 B45 I/O I/O ST ST RD7 RD8 55 42 84 68 C7 E9 A56 B37 I/O I/O ST ST RD9 RD10 43 44 69 70 E10 D11 A45 B38 I/O I/O ST ST RD11 RD12 45 — 71 79 C11 A9 A46 B43 I/O I/O ST ST RD13 RD14 — — 80 47 D8 L9 A54 B26 I/O I/O ST ST RD15 RE0 — 60 48 93 K9 A4 A31 B52 I/O I/O ST
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type A61 I/O ST E6 E3 B50 A7 I/O I/O ST ST 11 12 F4 F2 B6 A8 I/O I/O ST ST 8 — 14 96 F3 C3 A9 A65 I/O I/O ST ST RG13 RG14 — — 97 95 A3 C4 B55 B54 I/O I/O ST ST RG15 RG2 — 37 1 57 B2 H10 A2 B31 I/O I ST ST RG3 T1CK 36 48 56 74 J11 B11 A38 B40 I I ST ST Timer1 external clock input T2CK T3CK — — 6 7 D1 E4 A5 B4 I I ST ST Timer2 external clock input Timer3 external cl
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name Pin Type Buffer Type B5 I ST B39 O — SPI1 data out 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA SDI1 — 9 E1 SDO1 — 72 D9 Description SPI1 data in SS1 — 69 E10 A45 I/O ST SPI1 slave synchronization or frame pulse I/O SCK3 49 48 K9 A31 I/O ST Synchronous serial clock input/output for SPI3 SDI3 SDO3 50 51 52 53 K11 J10 A36 B29 I O ST — SPI3 data in SPI3 data out S
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B9 A26 I I ST ST JTAG Test mode select pin JTAG test clock input pin A40 B33 I O ST — JTAG test data input pin JTAG test data output pin E9 B37 O — Real-Time Clock alarm output L2 K3 A21 B17 I I Analog Comparator Voltage Reference (low) Analog Comparator Voltage Reference (high) 34 21 L5 H2 A24 B11 O I Analog Comparator Voltage Reference output Analog Comparator 1 negative input 11 2
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name Pin Type Buffer Type Description 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA PMD0 60 93 A4 B52 I/O PMD1 PMD2 61 62 94 98 B4 B3 A64 A66 I/O I/O PMD3 PMD4 63 64 99 100 A2 A1 B56 A67 I/O I/O TTL/ST Parallel Master Port data TTL/ST (Demultiplexed Master mode) or address/data (Multiplexed Master TTL/ST modes) TTL/ST TTL/ST PMD5 PMD6 1 2 3 4 D3 C1 B2 A4 I/O I/O TTL/ST TTL/ST PMD
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B4 B23 O I — ST Alternate CAN2 bus transmit pin Ethernet Receive Data 0(2) L7 K7 A28 B24 I I ST ST Ethernet Receive Data 1(2) Ethernet Receive Data 2(2) 44 L8 A29 I ST Ethernet Receive Data 3(2) 64 62 35 12 J5 F2 B20 A8 I I ST ST Ethernet receive error input(2) Ethernet receive data valid(2) ECRSDV ERXCLK 62 63 12 14 F2 F3 A8 A9 I I ST ST Ethernet carrier sense data valid(2) E
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B23 I ST A46 O — E9 B37 I/O — Alternate Ethernet carrier sense(2) Alternate Ethernet Management Data clock(2) Alternate Ethernet Management Data(2) C5 B51 O — Trace clock B55 O O — — Trace Data bits 0-3 A65 C4 B5 B54 A62 O O — — 25 K2 B14 I/O ST 15 24 K1 A15 I ST PGED2 18 27 J3 B16 I/O ST PGEC2 17 26 L1 A20 I ST MCLR 7 13 F1 B7 I/P ST AVDD 19 30
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 36 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 2.0 Note: 2.1 GUIDELINES FOR GETTING STARTED WITH 32-BIT MCUS This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION Tantalum or ceramic 10 µF ESR 3(3) R1 MCLR C VSS VCAP R VDD VDD 0.1 µF Ceramic VUSB3V3(1) PIC32 VDD VSS Connect(2) 0.1 µF Ceramic 0.1 µF Ceramic VSS VDD AVSS 0.1 µF Ceramic AVDD VDD VSS 0.1 µF Ceramic L1(2) Note 1: If the USB module is not used, this pin must be connected to VDD.
PIC32MX5XX/6XX/7XX 2.5 ICSP Pins 2.7 Trace The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PIC32MX5XX/6XX/7XX If your application needs to use certain ADC pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFG register during initialization of the ADC module. When MPLAB ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFG register. Automatic initialization of this register is only done during debugger operation.
PIC32MX5XX/6XX/7XX 3.0 Note: CPU This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS60001113) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.imgtec.com.
PIC32MX5XX/6XX/7XX 3.2 3.2.2 Architecture Overview The MIPS32 M4K processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e® Support Enhanced JTAG (EJTAG) Controller 3.2.
PIC32MX5XX/6XX/7XX The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair.
PIC32MX5XX/6XX/7XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS EJTAG debug single step. DINT EJTAG debug interrupt.
PIC32MX5XX/6XX/7XX 3.3 Power Management The MIPS32 M4K Processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction.
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 46 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space.
PIC32MX5XX/6XX/7XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L, PIC32MX664F064H AND PIC32MX664F064L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x
PIC32MX5XX/6XX/7XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Config
PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L, PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0
PIC32MX5XX/6XX/7XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0
PIC32MX5XX/6XX/7XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 KSEG1 0xBF8FFFFF Reserved Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0
PIC32MX5XX/6XX/7XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 Reserved 0xA001FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x
PIC32MX5XX/6XX/7XX TABLE 4-1: SFR MEMORY MAP Virtual Address Peripheral Base Offset Start Watchdog Timer 0x0000 RTCC 0x0200 Timer1-Timer5 0x0600 Input Capture 1-5 0x2000 Output Compare 1-5 0x3000 I2C1-I2C5 0x5000 SPI1-SPI4 0x5800 UART1-UART6 PMP 0xBF80 0x6000 0x7000 ADC 0x9000 CVREF 0x9800 Comparator 0xA000 Oscillator 0xF000 Device and Revision ID 0xF200 Flash Controller 0xF400 Reset 0xF600 Interrupts 0x1000 Bus Matrix 0x2000 DMA 0x3000 Prefetch 0xBF88 USB 0x4000
Control Registers Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code.
PIC32MX5XX/6XX/7XX REGISTER 4-1: Bit Range BMXCON: BUS MATRIX CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — — — — — — U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — BMX ERRIXI BMX ERRICD BMX ERRDMA BMX ERRDS BMX ERRIS U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-1 U-0 U-0 U-0 R/
PIC32MX5XX/6XX/7XX REGISTER 4-2: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<15:8> R-0 7:0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDKPBA<7:0> Legend: R = Re
PIC32MX5XX/6XX/7XX REGISTER 4-3: Bit Range 31:24 23:16 15:8 7:0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<15:8> R-0 R-0 BMXDUDBA<7:0> Legend: R = Readable
PIC32MX5XX/6XX/7XX REGISTER 4-4: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<15:8> R-0 7:0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDUPBA<7:0> Legend: R = Read
PIC32MX5XX/6XX/7XX REGISTER 4-5: Bit Range 31:24 23:16 15:8 7:0 BMXDRMSZ: DATA RAM SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXDRMSZ<31:24> R R BMXDRMSZ<23:16> R R R R R R R R BMXDRMSZ<15:8> R R BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is c
PIC32MX5XX/6XX/7XX REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXPFMSZ<31:24> R R R R R BMXPFMSZ<23:16> R R R R R BMXPFMSZ<15:8> R R R R R BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 62 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS60001121) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX5XX/6XX/7XX devices contain an internal Flash program memory for executing user code.
Control Registers Virtual Address (BF80_#) TABLE 5-1: FLASH CONTROLLER REGISTER MAP F400 NVMCON(1) F410 NVMKEY (1) F420 NVMADDR F430 NVMDATA F440 NVMSRC ADDR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — 31:16 — — — — — — — — — — — — 15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 NVMOP<3:0> NVMKEY<31:0> NVMADDR<31:0> NVMDATA<31:0> NVMSRCADDR<31:0> Legend: x
PIC32MX5XX/6XX/7XX REGISTER 5-1: Bit Range NVMCON: PROGRAMMING CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — — R/W-0, HC R/W-0 R-0, HS R-0, HS WR WREN WRERR(1) U-0 U-0 U-0 U-0 — — — — Legend: R = Readable bit -n = Value at POR — R-0, HSC (1) LVDERR(1) LVDSTAT
PIC32MX5XX/6XX/7XX REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Bit Bit 28/20/12/4 27/19/11/3 W-0 W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<23:16> W-0 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read
PIC32MX5XX/6XX/7XX REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATA: FLASH PROGRAM DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<23:16> R/W-0 NVMDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<7:0> Leg
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 68 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 6.0 Note: RESETS This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS60001118) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers Register Name(1) F600 RCON RESETS REGISTER MAP F610 RSWRST Bit Range Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — 15:0 — — — — — — CMR VREGS 31:16 — — — — — — — — 15:0 — — — — — — — — 23/7 20/4 19/3 18/2 17/1 16/0 22/6 21/5 — — — — — — — — EXTR SWR — WDTO SLEEP IDLE BOR POR 0000 — — — — — — — — 0000 — — — — — — — SWRST 0000 Legend: x = unknown value on Reset; — = unim
PIC32MX5XX/6XX/7XX REGISTER 6-1: Bit Range 31:24 23:16 15:8 7:0 RCON: RESET CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 — U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 — — — — — — CMR VREGS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR — WDTO SLEEP
PIC32MX5XX/6XX/7XX REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC — — — — — — — SWRST(1) Legend: HC = Cleared b
PIC32MX5XX/6XX/7XX 7.0 INTERRUPT CONTROLLER Note: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupts” (DS60001108) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> Highest Natural Order Priority CT – Core Timer Interrupt 0 0 CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26>
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location IRQ Number Vector Number AD1 – ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24> PMP – Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0> CMP1 – Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8> CMP2 – Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> U2E – UART2 Error SPI2E – SPI2 Fault I2C4B – I2C4 Bus Collision Ev
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority IC3E – Input Capture 3 Error 63 13 IFS1<31> IEC1<31> IPC3<12:10> IPC3<9:8> IC4E – Input Capture 4 Error 64 17 IFS2<0> IEC2<0> IPC4<12:10> IPC4<9:8> IC5E – Input Capture 5 Error 65 21 IFS2<1> IEC2<1> IPC5<12:10> IPC5<9:8> PMPE – Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1
Control Registers Register Name(1) TABLE 7-2: Virtual Address (BF88_#) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 IFS1 1050 IFS2 1060 IEC0 1070 IEC1 DS60001156J-page 77 1080 IEC2 1090 IPC0 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — 15:0 — — — — — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — —
Virtual Address (BF88_#) Register Name(1) 10A0 IPC1 INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES (CONTINUED) IPC2 10C0 IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 2009-2016 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS60001156J-page 79 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 15:0 — — — IC4IP<2:0> IC4IS<1:0>
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 1010 INTSTAT 1020 (3) IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS60001156J-page 81 10B0 IPC2 IPC3 10C0 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 10E0 IPC5 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 2009-2016 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES (3) 1010 INTSTAT 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 DS60001156J-page 83 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 28/12 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC4
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES 1010 INTSTAT 1020 (3) IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 DS60001156J-page 85 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 28/12 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 1010 INTSTAT 1020 (3) IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 DS60001156J-page 87 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> — — — T4IP<
PIC32MX5XX/6XX/7XX REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SS0 U-0 U-0 — — U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — MVEC — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1E
PIC32MX5XX/6XX/7XX REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 — — RIPL<2:0>(1) R/W-0 R/W-0 R/W-0 VEC<5:0>(1) Legend: R = Re
PIC32MX5XX/6XX/7XX REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS31 IFS30 IFS29 R/W-0 R/W-0 R/W-0 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 R/W-0 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS1
PIC32MX5XX/6XX/7XX REGISTER 7-6: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit ‘1’ = Bit is set R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP03<2:0> R/W-0 R/W-0 IS03<1:0> R/W-0 IP02<2:0> R/W-0 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) bit 12-10 IP01<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 9-8 bit 7-5 bit 4-2 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS01<1:0>: Interrupt Sub-priority bits 11 = Interrupt sub-priority is 3 10 = Interrupt sub-priority is 2 01 = Interrupt sub-priority is 1 00 = Interrupt sub-priority is 0 Unimplemented: Read as ‘0’ IP00<2:0>: Interrupt Priority
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 94 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 8.
Control Registers OSCTUN Bit Range Register Name(1) Bits F000 OSCCON F010 OSCILLATOR REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — 31:16 — — — — — — — 15:0 — — — — — — — PLLODIV<2:0> COSC<2:0> — 25/9 24/8 21/5 20/4 19/3 18/2 23/7 22/6 FRCDIV<2:0> — SOSCRDY — NOSC<2:0> CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN 0000 — — — — — — — — — 0000 — — — PBDIV<1:0> 17/1 16/0 PLLMULT<2:0> 0000 TUN<5:0> Legend: x = un
PIC32MX5XX/6XX/7XX REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 OSCCON: OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 R/W-y — — U-0 R-0 — U-0 R/W-y — Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-y R/W-0 R/W-0 R/W-1 R/W-y R/W-y PLLODIV<2:0> R-1 SOSCRDY PBDIVRDY R-0 Bit Bit 28/20/12/4 27/19/11/3 R-0 R/W-y FRCDIV<2:0> PBDIV<1:0> R-0 U-0 COSC<2:0> R/W-y R/W-y PLLMULT<2:0> R/W-y — R/W-y R/W-y NOSC<2:0> R/W-0 R-0 R-0 R/W-0 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast
PIC32MX5XX/6XX/7XX REGISTER 8-1: bit 2 bit 1 bit 0 Note: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) UFRCEN: USB FRC Clock Enable bit 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switc
PIC32MX5XX/6XX/7XX REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — R/W-0 (1) TUN<5:0> Legend: R = Readable bit W
PIC32MX5XX/6XX/7XX 9.0 PREFETCH CACHE Note: 9.1 • • • • This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Prefetch Cache” (DS60001119) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers Virtual Address (BF88_#) TABLE 9-1: 4010 CHEACC (1) CHETAG(1) 4030 CHEMSK(1) 4040 CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 4080 CHELRU 4090 CHEHIT 40A0 CHEMIS 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX REGISTER 9-1: Bit Range 31:24 23:16 15:8 7:0 CHECON: CACHE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CHECOH U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 — — PREFEN<1:0> — DCSZ<1:0> R/W-1 R/W-1 PFMWS<2:0>
PIC32MX5XX/6XX/7XX REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 CHEACC: CACHE ACCESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CHEWEN — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CHEIDX<3:0> Legend: R = Readab
PIC32MX5XX/6XX/7XX REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 CHETAG: CACHE TAG REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 LTAGBOOT — — — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x LTAG<19:12> R/W-x LTAG<11:4> R/W-x R/W-x R/W-x R/W-x LTAG<3:0> R/W-0 R/W-0 R/W-1 U-0 LVALID LLOCK LTYPE
PIC32MX5XX/6XX/7XX REGISTER 9-4: Bit Range 31:24 23:16 15:8 CHEMSK: CACHE TAG MASK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LMASK<10:3> R/W-0 7:0 R/W-0 R/W-0 LMASK<2:0> U-0 U-0 U-0 U-0 U-0 — — — — — Legend: R = Readab
PIC32MX5XX/6XX/7XX REGISTER 9-6: Bit Range CHEW1: CACHE WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 31:24 23:16 15:8 CHEW1<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<15:8> R/W-x R/W-x R/W-x R/W-x 7:0 R/W-x CHEW1<7:0> Legend: R = Readable bit
PIC32MX5XX/6XX/7XX REGISTER 9-8: Bit Range CHEW3: CACHE WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 31:24 23:16 15:8 CHEW3<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<15:8> R/W-x R/W-x R/W-x 7:0 R/W-x R/W-x CHEW3<7:0> Legend: R = Readable bit
PIC32MX5XX/6XX/7XX REGISTER 9-10: Bit Range CHEHIT: CACHE HIT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 31:24 23:16 15:8 CHEHIT<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<15:8> R/W-x R/W-x R/W-x R/W-x 7:0 R/W-x CHEHIT<7:0> L
PIC32MX5XX/6XX/7XX REGISTER 9-12: Bit Range CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x 31:24 23:16 15:8 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<15:8> R/W-x R/W-x R/W-x 7:0 R/W-x R/
PIC32MX5XX/6XX/7XX 10.0 Note: DIRECT MEMORY ACCESS (DMA) CONTROLLER This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS60001117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers Virtual Address (BF88_#) TABLE 10-1: DMASTAT 3020 DMAADDR 31/15 30/14 29/13 31:16 — — — 15:0 ON — — 31:16 — — — — 15:0 — — — — 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — RDWR SUSPEND DMABUSY 31:16 DMACH<2:0>(2) 0000 DMAADDR<31:0> 15:0 0000 x = unknown value on Reset; — = unimpl
Virtual Address (BF88_#) 3060 DCH0CON 3070 DCH0ECON 3080 3090 DCH0INT DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30F0 DCH0CSIZ 3100 DCH0CPTR DCH0DAT 3120 DCH1CON 3130 DCH1ECON 3140 DS60001156J-page 113 3150 DCH1INT DCH1SSA 3160 DCH1DSA 3170 DCH1SSIZ 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED 31:16 — — — — — — — — CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 31:16 — — — —
Virtual Address (BF88_#) DMA CHANNELS 0-7 REGISTER MAP (CONTINUED) 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 DCH2INT 3210 DCH2SSA 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 2009-2016 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 3290 DCH2DAT 32B0 DCH3ECON DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT 3360 DCH4CON 3370 DCH4ECON DS60001156J-page 115 3380 3390 DCH4INT DCH4SSA 33A0 DCH4DSA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS C
Virtual Address (BF88_#) 33C0 DCH4DSIZ 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR DCH4DAT 3420 DCH5CON 3430 DCH5ECON 3440 DCH5INT 3450 DCH5SSA 3460 DCH5DSA 3470 DCH5SSIZ 2009-2016 Microchip Technology Inc.
Virtual Address (BF88_#) 34D0 DCH5DAT 34E0 DCH6CON 34F0 DCH6ECON 3500 3510 DCH6INT DCH6SSA 3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3560 DCH6DPTR 3570 DCH6CSIZ 3580 DCH6CPTR DCH6DAT 35A0 DCH7CON 35B0 DCH7ECON DS60001156J-page 117 35C0 DCH7INT 35D0 DCH7SSA 35E0 DCH7DSA 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CH
Virtual Address (BF88_#) 3600 DCH7DSIZ 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR DCH7DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 15:0 — — — — — — — — 0000 —
PIC32MX5XX/6XX/7XX REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 ON(1) — — SUSPEND DMABUSY — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legen
PIC32MX5XX/6XX/7XX REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — RDWR DMACH<2:0> Legend: R = Readable bit W
PIC32MX5XX/6XX/7XX REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 BYTO<1:0> Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 R/W-0 (1) — — WBO — — BITO U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 U-0 U-0 PLEN<4:0> CRCEN CRCAPP(1) CR
PIC32MX5XX/6XX/7XX REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but not to the destination.
PIC32MX5XX/6XX/7XX REGISTER 10-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<7:0> L
PIC32MX5XX/6XX/7XX REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY — — — — — — CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 CHEN(2) CHAED
PIC32MX5XX/6XX/7XX REGISTER 10-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABOR
PIC32MX5XX/6XX/7XX REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED) bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag
PIC32MX5XX/6XX/7XX REGISTER 10-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> 23:16 R/W-0 R/W-0 CHSSA<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<15:8> 7:0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 10-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<15:8> 7:0 R/W-0 CHSSIZ<7:0> Lege
PIC32MX5XX/6XX/7XX REGISTER 10-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0 CHSPTR<7:0> Legend: R = Readable bit W = Wri
PIC32MX5XX/6XX/7XX REGISTER 10-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<15:8> 7:0 R/W-0 CHCSIZ<7:0> Legend
PIC32MX5XX/6XX/7XX REGISTER 10-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT<7:0> Legend: R =
PIC32MX5XX/6XX/7XX 11.0 Note: USB ON-THE-GO (OTG) This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB On-TheGo (OTG)” (DS60001126) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.
PIC32MX5XX/6XX/7XX FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) UFIN(5) Div x PLL Div 2 UFRCEN(3) OSC1 UPLLEN(6) UPLLIDIV(6) USB Suspend OSC2 To Clock Generator for Core and Peripherals Sleep or Idle (PB Out)(1) USB Module SRP Charge Bus USB Voltage Comparators SRP Discharge 48 MHz USB Clock(7) Full-Speed Pull-up D+(2) Registers and Control Interface Host Pull-do
Control Registers Register Name(1) TABLE 11-1: Virtual Address (BF88_#) 5040 U1OTGIR(2) 5050 U1OTGIE 5070 U1OTGCON 5080 U1PWRC U1IR(2) 5200 U1IE U1EIR(2) 5230 5240 U1EIE U1STAT(3) 5250 5260 DS60001156J-page 135 5270 U1CON U1ADDR U1BDTP1 Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 22/6 21/5 — — 20/4 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIF 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIE 31:16
Virtual Address (BF88_#) Register Name(1) 5280 U1FRML(3) 5290 U1FRMH(3) U1TOK 52B0 U1SOF 52C0 U1BDTP2 U1BDTP3 52E0 U1CNFG1 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 2009-2016 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 53A0 U1EP10 53B0 U1EP11 53C0 U1EP12 53D0 USB REGISTER MAP (CONTINUED) U1EP13 53E0 U1EP14 53F0 U1EP15 Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 0000 15:0 — — — — — — — — —
PIC32MX5XX/6XX/7XX REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0,
PIC32MX5XX/6XX/7XX REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTV
PIC32MX5XX/6XX/7XX REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID — LSTATE — SESVD SESEND — VBUSVD Legend:
PIC32MX5XX/6XX/7XX REGISTER 11-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 DPPULUP DMPULUP DPPULDWN DMPULDWN R/W-0 R/W-0 R/W-0 R/W-0 V
PIC32MX5XX/6XX/7XX REGISTER 11-5: U1PWRC: USB POWER CONTROL REGISTER Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND — — USLPGRD USBBUSY — USUSPEND
PIC32MX5XX/6XX/7XX REGISTER 11-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 IDLEIF TRNIF(3) SOFIF
PIC32MX5XX/6XX/7XX REGISTER 11-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE
PIC32MX5XX/6XX/7XX REGISTER 11-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS
PIC32MX5XX/6XX/7XX REGISTER 11-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE DMAEE BTOEE
PIC32MX5XX/6XX/7XX REGISTER 11-10: U1STAT: USB STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI — — ENDPT<3:0> Legend: R = Readable bit W =
PIC32MX5XX/6XX/7XX REGISTER 11-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 PKTDIS(4) TOKBUSY(1,5) USBRST HOSTEN(2)
PIC32MX5XX/6XX/7XX REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the Even buffer descriptor banks 0 = Even/Odd buffer pointers are not reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry is enabled 0 = USB module and supporting circuitry is disabled SOFEN: SOF Enable bit(5) 1 = SOF token is sent every 1 ms 0 = SOF token is disabled Note 1: 2: 3: 4: 5: Software is required to ch
PIC32MX5XX/6XX/7XX REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR<6:0> Legend: R = Readable
PIC32MX5XX/6XX/7XX REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — FRMH<2:0> Legend: R = Readable b
PIC32MX5XX/6XX/7XX REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CNT<7:0> Legend: R = Readable bit
PIC32MX5XX/6XX/7XX REGISTER 11-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 BDTPTRH<23:16> L
PIC32MX5XX/6XX/7XX REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 UTEYE UOEMON — USBSIDL — — — UASUS
PIC32MX5XX/6XX/7XX REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS — EPCONDIS
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 156 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 12.0 I/O PORTS Note: Following are some of the key features of this module: • Individual output pin open-drain enable/disable • Individual input pin weak pull-up enable/disable • Monitor selective inputs and generate interrupt when change in pin state is detected • Operation during Sleep and Idle modes • Fast bit manipulation using CLR, SET and INV registers Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port.
PIC32MX5XX/6XX/7XX 12.1 Parallel I/O (PIO) Ports All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a Data Direction or Tri-State Control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1, configures the corresponding I/O pin as an input; setting a TRISx register bit = 0, configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset.
Control Registers Register Name(1) TABLE 12-1: Virtual Address (BF88_#) 6000 TRISA 6010 PORTA 6020 LATA PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 6030 ODCA 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — —
Virtual Address (BF88_#) Register Name(1) 6080 TRISC PORTC 60A0 LATC 60B0 ODCC 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx 31:16 — — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 60C0 TRISD PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 60D0 PORTD 60E0 LATD 60F0 ODCD 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 31:16 — — — — — — — — — — — — — — — — 15:0
Virtual Address (BF88_#) Register Name(1) 6100 TRISE PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 6110 PORTE 6120 LATE 6130 ODCE 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — — — — — — — — — 15:0
Virtual Address (BF88_#) Register Name(1) 6140 TRISF PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 6150 PORTF 6160 LATF 6170 ODCF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — TRISF5 31:16 —
Virtual Address (BF88_#) Register Name(1) 6180 TRISG 6190 PORTG 61A0 61B0 LATG ODCG 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 31:16 — — — — — — — — 15:0 — — — — — — TRISG9 TRISG8 — — — — TRISG7 TRISG6 — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — RG9 RG8 RG7 RG6 — 31:16 — — — — — — — — — — 15:0 — — — — — — LATG9 LATG8 LATG7 31:16 — — — — — — — — 15:0 — — — — — — ODCG9 ODCG8
Virtual Address (BF88_#) 61C0 CNCON 61D0 CNEN 61E0 CNPUE 31/15 30/14 31:16 — 15:0 ON 31:16 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — 0000 — SIDL — — — — — — — — — — — — — 0000 — — — — — — — — — — CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000 31
PIC32MX5XX/6XX/7XX REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 CNCON: CHANGE NOTICE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON — SIDL — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readab
PIC32MX5XX/6XX/7XX 13.0 Note: TIMER1 13.1 Additional Supported Features • Selectable clock prescaler • Timer operation during Idle and Sleep mode • Fast bit manipulation using CLR, SET and INV registers • Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
Control Registers Virtual Address (BF80_#) TABLE 13-1: TIMER1 REGISTER MAP 0600 T1CON 0610 TMR1 0620 PR1 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — 15:0 ON — SIDL 31:16 — — — — — — — — TWDIS TWIP — — — — — 15:0 31:16 15:0 23/7 22/6 21/5 20/4 19/3 — — — — — — — TGATE — TCKPS<1:0> — — — — — — — — — — — 18/2 17/1 16/0 — — — 0000 TSYNC TCS — 0000 — — — 0000 — — — TMR1<15:0> — — — — — — — — — 0000 PR1<15
PIC32MX5XX/6XX/7XX REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 ON(1) — SIDL TWDIS TWIP — — — R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 TGATE — — TSYNC
PIC32MX5XX/6XX/7XX REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored.
PIC32MX5XX/6XX/7XX 14.0 TIMER2/3, TIMER4/5 Note: Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
PIC32MX5XX/6XX/7XX FIGURE 14-2: TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy MS Half Word ADC Event Trigger(3) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx PRx 0 1 Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) TGATE (TxCON<7>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’
Control Registers TABLE 14-1: Virtual Address (BF80_#) TIMER2 THROUGH TIMER5 REGISTER MAP 0800 T2CON 0810 TMR2 0820 PR2 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — 15:0 ON 31:16 — — — — — — — — SIDL — — — — — — — — — — 15:0 31:16 0A10 TMR3 0A20 PR3 — — — — — — — 0C20 PR4 TMR5 0E20 PR5 — — — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 — — — — — — — — — — — — — — — —
PIC32MX5XX/6XX/7XX REGISTER 14-1: Bit Range 31:24 23:16 15:8 7:0 TXCON: TYPE B TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(1,3) — SIDL(4) — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 T32(2) — TCS(3) —
PIC32MX5XX/6XX/7XX REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) bit 3 T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: When using the 1:1 PBCLK divisor, the user’s software should
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 176 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 15.0 WATCHDOG TIMER (WDT) Note: This section describes the operation of the WDT and Power-up Timer of the PIC32MX5XX/6XX/7XX. This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8.
Control Registers WATCHDOG TIMER REGISTER MAP 0000 WDTCON Bit Range Register Name(1) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 ON — — — — — — — — 20/4 19/3 18/2 17/1 — — — — — 0000 — WDTCLR 0000 SWDTPS<4:0> 16/0 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MX5XX/6XX/7XX REGISTER 15-1: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ON(1,2) — — — — — — — U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0 — SWDTPS<4:0> WDTWINEN WDTCLR Leg
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 180 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 16.0 Note: INPUT CAPTURE • Capture timer value on every edge (rising and falling) • Capture timer value on every edge (rising and falling), specified edge first. • Prescaler capture event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source.
Control Registers Virtual Address (BF80_#) Register Name TABLE 16-1: 2000 IC1CON(1) 2010 IC1BUF 2200 IC2CON(1) 2210 IC2BUF 2400 IC3CON(1) 2410 IC3BUF 2600 IC4CON(1) 2610 IC4BUF 2800 IC5CON(1) 2810 IC5BUF INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — 15:0 ON 25/9 — — — — — — — SIDL — — — FEDGE 31:16 31:16 — — — — — — — 15:0 ON — SIDL — — — FEDGE 31:16 22/6 21/5 — — — — C32 ICTMR ICI<1:0> 20/4
PIC32MX5XX/6XX/7XX REGISTER 16-1: Bit Range Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 — — — 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 ON(1) — SIDL — — — FEDGE C32 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 ICOV ICBNE IC
PIC32MX5XX/6XX/7XX REGISTER 16-1: bit 2-0 Note 1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER (CONTINUED) ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode – every sixteenth rising edge 100 = Prescaled Capture Event mode – every fourth rising edge 011 = Simple Capture Event mode – every rising edge 010 = Simple Ca
PIC32MX5XX/6XX/7XX 17.0 Note: OUTPUT COMPARE The following are key features of the Output Compare module: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Output Compare” (DS60001111) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers Virtual Address (BF80_#) TABLE 17-1: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP 3000 OC1CON 3010 OC1R 3020 OC1RS 3200 OC2CON 3210 OC2R 3220 OC2RS 3400 OC3CON 3410 OC3R 3420 OC3RS 3600 OC4CON 3610 OC4R 3620 OC4RS 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 ON(1) — SIDL — — — — — U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC32 OCFLT(2) O
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 188 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 18.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) The following are some of the key features of the SPI module: • • • • This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (DS60001106) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.
Control Registers Virtual Address (BF80_#) TABLE 18-1: 5E10 SPI1STAT(2) 5E20 SPI1BUF(2) 5E30 SPI1BRG(2) 5800 SPI3CON 5810 SPI3STAT 5820 SPI3BUF 5830 SPI3BRG 5A00 SPI2CON 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPIFE ENHBUF(2) FRMCNT<2:0> R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON(1) — SIDL DISSDO MODE32 MODE16 SMP CK
PIC32MX5XX/6XX/7XX REGISTER 18-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode bit 12 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module (pin is controlled by associated PORT register) 0 = SDOx pin is controlled by the module bit 11-10 MODE<32,16
PIC32MX5XX/6XX/7XX REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 R-0 SPITUR — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 RXBUFELM<4:0> R-0 TXBUFELM<4:0> U-0 R-0 U-0 — — — — SPIBUSY — — R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE — SPITBE — SPITBF SP
PIC32MX5XX/6XX/7XX REGISTER 18-2: bit 1 SPIxSTAT: SPI STATUS REGISTER SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
PIC32MX5XX/6XX/7XX 19.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX FIGURE 19-1: I2C BLOCK DIAGRAM Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop bit Detect Write Start and Stop bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS60001156J-page 196 2009-2016 Microchip Techno
Control Registers Register Name(1) TABLE 19-1: Virtual Address (BF80_#) 5000 I2C3CON 5010 I2C3STAT 5020 I2C3ADD I2C3MSK 5040 I2C3BRG 5050 I2C3TRN I2C3RCV 5100 I2C4CON 5110 I2C4STAT 5120 I2C4ADD 5130 I2C4MSK 5140 I2C4BRG DS60001156J-page 197 5150 I2C4TRN 5160 I2C4RCV 5200 I2C5CON I2C5STAT 5220 I2C5ADD 31/15 30/14 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 ON — SIDL SCLREL ST
Virtual Address (BF80_#) Register Name(1) 5230 I2C5MSK I2C5BRG 5250 I2C5TRN 5260 I2C5RCV 5300 I2C1CON I2C1STAT 5320 I2C1ADD 5330 I2C1MSK 5340 I2C1BRG 5350 I2C1TRN 5360 I2C1RCV 5400 I2C2CON(2) 5410 I2C2STAT(2) 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2C CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 ON(1) — SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, H
PIC32MX5XX/6XX/7XX REGISTER 19-1: I2CXCON: I2C CONTROL REGISTER (CONTINUED) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit.
PIC32MX5XX/6XX/7XX REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0
PIC32MX5XX/6XX/7XX REGISTER 19-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED) bit 5 D_A: Data/Address bit (when operating as I2C slave) This bit is cleared by hardware upon a device address match, and is set by hardware by reception of the slave byte. 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address bit 4 P: Stop bit This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
PIC32MX5XX/6XX/7XX 20.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX Figure 20-2 and Figure 20-3 illustrate typical receive and transmit timing for the UART module.
Control Registers TABLE 20-1: Virtual Address (BF80_#) UART1 THROUGH UART6 REGISTER MAP 6000 U1MODE(1) 6010 U1STA(1) 6020 U1TXREG 6030 U1RXREG 6040 U1BRG(1) 6200 U4MODE(1) (1) U4STA 6220 U4TXREG 6230 U4RXREG 6240 (1) U4BRG U3STA(1) DS60001156J-page 205 6420 U3TXREG 6430 U3RXREG 6440 U3BRG(1) 6600 U6MODE (1) U6STA(1) 6610 29/13 31:16 — — — 15:0 ON — SIDL 31:16 — — — 28/12 27/11 26/10 25/9 24/8 — — — — — IREN RTSMD — — — — — ADM_EN UEN<1:0> 15:0
Virtual Address (BF80_#) Register Name 6620 U6TXREG 6630 U6RXREG U6BRG(1) 6800 U2MODE(1) U2STA(1) 6810 U2TXREG 6830 U2RXREG 6840 U2BRG(1) 6A00 U5MODE(1) 6A10 U5STA(1) 6A20 U5TXREG 6A30 U5RXREG U5BRG(1) 6A40 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — 15:0 — — — — — — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — 31:16 — — — — — — — RX8 — — — — 31:16 — — — — — — — — 15:0 ON — SID
PIC32MX5XX/6XX/7XX REGISTER 20-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 ON(1) — SIDL IREN RTSMD — R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH Legend
PIC32MX5XX/6XX/7XX REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed mode – 16x b
PIC32MX5XX/6XX/7XX REGISTER 20-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 TRMT ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0, HC R/W-0 UTXINV URXEN UTXBRK UTXEN UTXBF R
PIC32MX5XX/6XX/7XX REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
PIC32MX5XX/6XX/7XX 21.0 PARALLEL MASTER PORT (PMP) Note: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS60001128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 21-1: 7000 PMCON PARALLEL MASTER PORT REGISTER MAP 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 PMDIN 7050 PMAEN 7060 PMSTAT 31/15 30/14 29/13 31:16 — — — 15:0 ON — SIDL 31:16 — — — 15:0 BUSY 31:16 — IRQM<1:0> — — 28/12 27/11 — — ADRMUX<1:0> — — INCM<1:0> — — 26/10 25/9 24/8 23/7 22/6 — — — — — PMPTTL PTWREN PTRDEN — — — MODE16 — MODE<1:0> — — 15:0 CS2EN/A15 CS1EN/A14 — — — 19/3 18/
PIC32MX5XX/6XX/7XX REGISTER 21-1: Bit Range 31:24 23:16 15:8 7:0 PMCON: PARALLEL PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 U-0 R/W-0 ON(1) — SIDL ADRMUX<1:0> R/W-0 R/W-0 (2) R/W-0 (2) U-0 CSF<1:0> ALP — R/W-0 R/W-0 R/W-0 PMPTTL PTWREN PT
PIC32MX5XX/6XX/7XX REGISTER 21-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 3 CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) bit 2 Unimplemented: Read as ‘0’ bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Rea
PIC32MX5XX/6XX/7XX REGISTER 21-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 (1) R/W-0 WAITB<1:0> INCM<1:0> R/W-0 R/W-0 (1) — MODE<1:0> R/W-0 R
PIC32MX5XX/6XX/7XX REGISTER 21-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB • • • 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note 1: Whenev
PIC32MX5XX/6XX/7XX REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) R/W-0 (3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 CS1 ADDR15(2) ADDR14(4) R/W-0 R/W-0 ADDR<13:8> R/W-0 R/W-0 R/
PIC32MX5XX/6XX/7XX REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — PTEN14 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<10:8> R/W-0 R/W-0 R/W-0 PTEN<7:0> Lege
PIC32MX5XX/6XX/7XX REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (ONLY SLAVE MODES) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0, HS, SC U-0 U-0 R-0 R-0 R-0 R-0 IB0F IBF IBOV — — IB3F IB2F IB1F R-1 R/W-0, HS, SC U-0 U-0 R-1 R-1 R-1
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 220 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 22.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 22-1: 0200 RTCCON RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — 15:0 ON — — — — — — SIDL — — — 31:16 — — — — 15:0 ALRMEN CHIME PIV ALRMSYNC 31:16 25/9 24/8 — — — — — — SEC10<3:0> SEC01<3:0> YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 HR10<3:0> HR01<3:0> 15:0 SEC10<3:0> — — DAY10<3:0> RTSECSEL RTCCLKON — — —
PIC32MX5XX/6XX/7XX REGISTER 22-1: Bit Range 31:24 23:16 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit 29/21/13/5 28/20/12/4 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CAL<9:8> CAL<7:0> 15:8 7:0 RTCCON: RTC CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 ON(1,2) — SIDL — — — — — R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0 — — RTSECSEL(3) RTCCLKON L
PIC32MX5XX/6XX/7XX REGISTER 22-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read.
PIC32MX5XX/6XX/7XX REGISTER 22-2: Bit Range 31:24 23:16 15:8 RTCALRM: RTC ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (2) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 PIV ALRMSYNC(3) R/W-0 AMA
PIC32MX5XX/6XX/7XX REGISTER 22-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(2) 11111111 = Alarm will trigger 256 times bit 7-0 • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
PIC32MX5XX/6XX/7XX REGISTER 22-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — SEC10<3:0> R/W-x R/W-x
PIC32MX5XX/6XX/7XX REGISTER 22-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x YEAR01<3:0> MONTH10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x U-0 U-0 R/W-x R/W-x — — DAY10<3:0> R/W-x R/W-x DAY01<3:0
PIC32MX5XX/6XX/7XX REGISTER 22-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — SEC10<3:0> R/W-x R/
PIC32MX5XX/6XX/7XX REGISTER 22-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 U-0 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 — — — — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 R/W-x R/W-x — — — — MONTH10<3:0> R/W-x MONTH01<3:0> DAY10<1:0> R/W-x R/W-x DAY01<3:0> R/W-x R/W-x
PIC32MX5XX/6XX/7XX 23.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 23-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC 2 1 TAD ADCS<7:0> 0 8 TPB ADC Conversion Clock Multiplier 2, 4,..., 512 DS60001156J-page 232 2009-2016 Microchip Technology Inc.
Control Registers TABLE 23-1: Virtual Address (BF80_#) ADC REGISTER MAP 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS (1) 9060 AD1PCFG(1) 9050 AD1CSSL(1) 9070 ADC1BUF0 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 DS60001156J-page 233 90F0 ADC1BUF8 9100 ADC1BUF9 9110 ADC1BUFA 30/14 29/13 28/12 27/11 26/10 31:16 — 15:0 ON 31:16 — — — — — — SIDL — — — — — — — — — — — — 15:0 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — B
Virtual Address (BF80_#) ADC REGISTER MAP (CONTINUED) 9120 ADC1BUFB 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) Legend: x = unknown value on Reset; — = unimplemen
PIC32MX5XX/6XX/7XX REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 AD1CON1: ADC CONTROL REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 ON(1) — SIDL — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CLRASAM — ASAM SSRC<2:0> FORM<2:0> R/W-0, HS
PIC32MX5XX/6XX/7XX REGISTER 23-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated.
PIC32MX5XX/6XX/7XX REGISTER 23-2: Bit Range 31:24 23:16 15:8 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 OFFCAL — CSCNA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ALTS VCFG<2:0> 7:0 Bit Bit 28/20/12/4 27/19/11/3 R-0 U-0 BUFS — R/W-0 S
PIC32MX5XX/6XX/7XX REGISTER 23-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W R/W-0 SAMC<4:0>(1) R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) Legend: R = Read
PIC32MX5XX/6XX/7XX REGISTER 23-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — — R/W-0 U-0 U-0 U-0 CH0SB<3:0> CH0NA — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 CH0SA<3:0> Leg
PIC32MX5XX/6XX/7XX REGISTER 23-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX 24.0 Note: CONTROLLER AREA NETWORK (CAN) This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. “Controller Area Network (CAN)” (DS60001154) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers Virtual Address (BF88_#) Register Name(1) TABLE 24-1: B000 C1CON C1CFG B020 C1INT B030 B050 B060 C1VEC C1TREC C1FSTAT C1RXOVF B070 B080 C1TMR C1RXM0 2009-2016 Microchip Technology Inc.
Virtual Address (BF88_#) B0F0 C1FLTCON3 B100 C1FLTCON4 B110 C1FLTCON5 B120 C1FLTCON6 B130 C1FLTCON7 B140 C1RXFn (n = 0-31) C1FIFOBA C1FIFOINTn (n = 0-31) 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range 29/13 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000 15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000 31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 15:0 FLTEN1
Virtual Address (BF88_#) Register Name(1) C000 C2CON C010 C2CFG C040 C050 C060 C070 C2INT C2VEC C2TREC C2FSTAT C2RXOVF C2TMR C080 C2RXM0 C0A0 C2RXM1 C0B0 2009-2016 Microchip Technology Inc.
Virtual Address (BF88_#) C100 C2FLTCON4 C110 C2FLTCON5 C120 C2FLTCON6 C130 C2FLTCON7 C140 C340 CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) C2RXFn (n = 0-31) C2FIFOBA C380 29/13 28/12 27/11 26/10 25/9 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000
PIC32MX5XX/6XX/7XX REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 CiCON: CAN MODULE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 S/HC-0 R/W-1 — — — — ABAT R-0 R-0 R-1 OPMOD<2:0> R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 REQOP<2:0> R/W-0 U-0 U-0 U-0 CANCAP — — — U-0 — U-0 R-0 U-0 U-0 U-0 U-0 R/W-0 ON(1) — SIDLE — CANBUSY — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 24-1: CiCON: CAN MODULE CONTROL REGISTER (CONTINUED) bit 13 SIDLE: CAN Stop in Idle bit 1 = CAN Stops operation when system enters Idle mode 0 = CAN continues operation when system enters Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 CANBUSY: CAN Module is Busy bit 1 = The CAN module is active 0 = The CAN module is completely disabled bit 10-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits 10011-11111 = Invalid Selection (compare
PIC32MX5XX/6XX/7XX REGISTER 24-2: Bit Range 31:24 23:16 15:8 7:0 CiCFG: CAN BAUD RATE CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — WAKFIL — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS (1) (2) SAM R/W-0 R/W-0 SEG2PH<2:0>(1,4) SEG1PH<2:0> R/W-0 R/W-0 (3)
PIC32MX5XX/6XX/7XX REGISTER 24-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED) bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4) 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3) 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FSYS 111110 = TQ = (2 x 63)/FSYS • • • 000001 = TQ = (2 x 2)/FSYS 000000 = TQ = (2 x 1)/FSYS Note 1:
PIC32MX5XX/6XX/7XX REGISTER 24-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 CiINT: CAN INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — MODIE CTMRIE RBIE TBIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 (1) IVRIF WAKIF CERRIF RBOVIF — — — U-0 U-0 U-
PIC32MX5XX/6XX/7XX REGISTER 24-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED) bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = A bus wake-up activity interrupt has occurred 0 = A bus wake-up activity interrupt has not occurred bit 13 CERRIF: CAN Bus Error Interrupt Flag bit 1 = A CAN bus error has occurred 0 = A CAN bus error has not occurred bit 12 SERRIF: System Error Interrupt Flag bit 1 = A system error occurred (typically an illegal address was presented to the system bus) 0 = A syste
PIC32MX5XX/6XX/7XX REGISTER 24-4: Bit Range CiVEC: CAN INTERRUPT CODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 23:16 15:8 7:0 — — — U-0 R-1 R-0 FILHIT<4:0> R-0 (1) — ICODE<6:0> Legend: R = Readable bit W = Writa
PIC32MX5XX/6XX/7XX REGISTER 24-5: Bit Range 31:24 23:16 15:8 7:0 CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWARN RXWARN EWARN R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> R-0 RERRCNT<7:0> Legend: R =
PIC32MX5XX/6XX/7XX REGISTER 24-7: Bit Range CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER Bit 31/23/15/7 31:24 23:16 15:8 7:0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R-0 R-0 R-0 R-0 R-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 Bit 26/18/10/2 Bit 25/17/9/1 R-0 R-0 RXOVF26 RXOVF25 R-0 Bit 24/16/8/0 R-0 RXOVF24 R-0 R-0 R-0 R-0 R-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RX
PIC32MX5XX/6XX/7XX REGISTER 24-9: Bit Range 31:24 23:16 15:8 7:0 CiRXMn: CAN ACCEPTANCE FILTER MASK ‘n’ REGISTER (n = 0, 1, 2 OR 3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SID<10:3> R/W-0 R/W-0 R/W-0 SID<2:0> U-0 R/W-0 U-0 — MIDE — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EID<17:
PIC32MX5XX/6XX/7XX REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN3 R/W-0 23:16 FLTEN2 R/W-0 15:8 FLTEN1 R/W-0 7:0 FLTEN0 MSEL3<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL2<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL1<1:0> R/W-0 Bit 25/17/9/1 FSEL3<4:0> MSEL2<1:0> R/W-
PIC32MX5XX/6XX/7XX REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED) bit 15 FLTEN1: Filter 1 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL1<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 •
PIC32MX5XX/6XX/7XX REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN7 R/W-0 23:16 FLTEN6 R/W-0 15:8 FLTEN5 R/W-0 7:0 FLTEN4 MSEL7<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL6<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL5<1:0> R/W-0 Bit 25/17/9/1 FSEL7<4:0> MSEL6<1:0> R/W-
PIC32MX5XX/6XX/7XX REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED) bit 15 FLTEN5: Filter 17 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL5<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 • •
PIC32MX5XX/6XX/7XX REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN11 R/W-0 23:16 FLTEN10 R/W-0 15:8 FLTEN9 R/W-0 7:0 FLTEN8 MSEL11<1:0> R/W-0 R/W-0 FSEL11<4:0> R/W-0 R/W-0 MSEL10<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL9<1:0> R/W-0 R
PIC32MX5XX/6XX/7XX REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED) bit 15 FLTEN9: Filter 9 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL9<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 •
PIC32MX5XX/6XX/7XX REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN15 R/W-0 23:16 FLTEN14 R/W-0 15:8 FLTEN13 R/W-0 7:0 FLTEN12 MSEL15<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL14<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL13<1:0> R/W-0 Bit 25/17/9/1 FSEL15<4:0> MSEL14<1:0>
PIC32MX5XX/6XX/7XX REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED) bit 15 FLTEN13: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL13<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer
PIC32MX5XX/6XX/7XX ,4 REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 FLTEN19 R/W-0 23:16 FLTEN18 R/W-0 15:8 FLTEN17 R/W-0 7:0 FLTEN16 MSEL19<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL18<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL17<1:0> R/W-0 Bit 25/17/9/1 FSEL19<4:0> MSEL18<
PIC32MX5XX/6XX/7XX REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED) bit 15 FLTEN17: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL17<1:0>: Filter 17 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL17<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer
PIC32MX5XX/6XX/7XX REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN23 R/W-0 23:16 FLTEN22 R/W-0 15:8 FLTEN21 R/W-0 7:0 FLTEN20 MSEL23<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL22<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL21<1:0> R/W-0 Bit 25/17/9/1 FSEL23<4:0> MSEL22<1:0>
PIC32MX5XX/6XX/7XX REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED) bit 15 FLTEN21: Filter 21 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL21<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer
PIC32MX5XX/6XX/7XX REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN27 R/W-0 23:16 FLTEN26 R/W-0 15:8 FLTEN25 R/W-0 7:0 FLTEN24 MSEL27<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL26<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL25<1:0> R/W-0 Bit 25/17/9/1 FSEL27<4:0> MSEL26<1:0>
PIC32MX5XX/6XX/7XX REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED) bit 15 FLTEN25: Filter 25 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL25<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30
PIC32MX5XX/6XX/7XX REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN31 R/W-0 23:16 FLTEN30 R/W-0 15:8 FLTEN29 R/W-0 7:0 FLTEN28 MSEL31<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL30<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL29<1:0> R/W-0 Bit 25/17/9/1 FSEL31<4:0> MSEL30<1:0>
PIC32MX5XX/6XX/7XX REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED) bit 15 FLTEN29: Filter 29 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL29<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30
PIC32MX5XX/6XX/7XX REGISTER 24-18: CiRXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER 7 (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID<10:3> R/W-x R/W-x R/W-x SID<2:0> U-0 R/W-0 U-0 — EXID — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<17:16>
PIC32MX5XX/6XX/7XX REGISTER 24-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0(1) CiFIFOBA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<15:8> R/
PIC32MX5XX/6XX/7XX REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 S/HC-0 S/HC-0 U-0 U-0 FSIZE<4:0>(1) R/W-0 DONLY U-0 (1) U-0 — FRESET UINC — — — — R/W-0 R-0 R-0 R-0 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31) bit 6 TXABAT: Message Aborted bit(2) 1 = Message was aborted 0 = Message completed successfully bit 5 TXLARB: Message Lost Arbitration bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Error Detected During Transmission bit(3) 1 = A bus error occured while the message was being sent 0 = A bus error did not occur while the message was being
PIC32MX5XX/6XX/7XX REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31) Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 31:24 23:16 15:8 7:0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — TXNFULLIF(1
PIC32MX5XX/6XX/7XX REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31) bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is half full 0 = FIFO is > half full TXEN = 0: (FIFO configured as a receive buffer) Unused, reads ‘0’ bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is empty 0 = FIFO is not empty, at least 1 message queued to be
PIC32MX5XX/6XX/7XX REGISTER 24-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-0(1) R-0(1) CiFIFOUAn<31:24> R-x R-x R-x R-x R-x R-x CiFIFOUAn<15:8> R-x R-x R-x R-x R-x CiFIFOUAn<7:0> Legend: R = Readable bit -n = Value at POR
PIC32MX5XX/6XX/7XX 25.0 ETHERNET CONTROLLER Note: Key features of the Ethernet Controller include: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. “Ethernet Controller” (DS60001155) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX Table 25-1, Table 25-2, Table 25-3 and Table 25-4 show four interfaces and the associated pins that can be used with the Ethernet Controller.
Control Registers Register Name(1) TABLE 25-5: Virtual Address (BF88_#) 9000 ETHCON1 9010 ETHCON2 9020 ETHTXST 9030 ETHRXST 9040 ETHHT0 9050 ETHHT1 9060 ETHPMM0 9070 ETHPMM1 9080 ETHPMCS 9090 ETHPMO ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F
Virtual Address (BF88_#) Register Name(1) 90E0 ETHSTAT ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 9260 EMAC1 SUPP ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — All Res
PIC32MX5XX/6XX/7XX REGISTER 25-1: Bit Range 31:24 23:16 15:8 7:0 ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 Bit 31/23/15/7 R/W-0 Bit Bit 30/22/14/6 29/21/13/5 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTV<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTV<7:0> R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ON — SIDL — — — TXRTS RXEN(1) R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 AUTOFC —
PIC32MX5XX/6XX/7XX REGISTER 25-1: bit 7 ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED) AUTOFC: Automatic Flow Control bit 1 = Automatic Flow Control is enabled 0 = Automatic Flow Control is disabled Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to automatically enable and disable the Flow Control, respectively. When the number of received buffers BUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled.
PIC32MX5XX/6XX/7XX REGISTER 25-2: Bit Range ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2 Bit 31/23/15/7 31:24 23:16 15:8 7:0 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — — — RXBUFSZ<3:0> RXBUFSZ<6
PIC32MX5XX/6XX/7XX REGISTER 25-3: Bit Range 31:24 23:16 15:8 7:0 ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — TXSTADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<15:8> R/W-0 R
PIC32MX5XX/6XX/7XX REGISTER 25-5: Bit Range ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 HT<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 HT<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HT<15:8> 7:0 R/W-0 HT<7:0> L
PIC32MX5XX/6XX/7XX REGISTER 25-7: Bit Range 31:24 ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 31-24 bit 23-16 bit 15-8 bit 7-0 Note 1: 2: R/W-0 R/W-0 W = Writable bit ‘1’ = Bit is s
PIC32MX5XX/6XX/7XX REGISTER 25-9: Bit Range 31:24 23:16 15:8 7:0 ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 Note 1: 2: U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMCS<15:8> R/W-0 PMCS<7:0> Legend: R = Rea
PIC32MX5XX/6XX/7XX REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit Bit 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HTEN MPEN — NOTPM R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MX5XX/6XX/7XX REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER (CONTINUED) bit 7 bit 6 bit 5 bit 4 CRCERREN: CRC Error Collection Enable bit 1 = The received packet CRC must be invalid for the packet to be accepted 0 = Disable CRC Error Collection filtering This bit allows the user to collect all packets that have an invalid CRC.
PIC32MX5XX/6XX/7XX REGISTER 25-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 31:24 23:16 RXFWM<7:0> U-0 15:8 7:0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXEWM<7:0
PIC32MX5XX/6XX/7XX REGISTER 25-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 — R/W-0 TXBUSEIE(1) RXBUSEIE(2) R/W-0 R/W-0 RXDONEIE(2) PKTPENDIE
PIC32MX5XX/6XX/7XX REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 — TXBUSE RXBUSE — — — EWMARK FWMARK R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER bit 6 PKTPEND: Packet Pending Interrupt bit 1 = RX packet pending in memory 0 = RX packet is not pending in memory This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or by writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
PIC32MX5XX/6XX/7XX REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 BUFCNT<7:0> U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ETHBUSY(1) TXBUSY(2) RXBUSY(2)
PIC32MX5XX/6XX/7XX REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED) bit 5 RXBUSY: Receive Busy bit(2) 1 = RX logic is receiving data 0 = RX logic is idle This bit indicates that a packet is currently being received. A change in this status bit is not necessarily reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter. bit 4-0 Unimplemented: Read as ‘0’ Note 1: 2: This bit will be set when the ON bit (ETHCON1<15>) = 1.
PIC32MX5XX/6XX/7XX REGISTER 25-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 RXOVFLWCNT<15:8> R/W-0
PIC32MX5XX/6XX/7XX REGISTER 25-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMTXOKCNT<15:8> R/
PIC32MX5XX/6XX/7XX REGISTER 25-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 SCOLFRMCNT<15:8>
PIC32MX5XX/6XX/7XX REGISTER 25-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 24/16/8/0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MCOLFRMCNT<15:
PIC32MX5XX/6XX/7XX REGISTER 25-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMRXOKCNT<15:8> R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 25-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FCSERRCNT<15:8>
PIC32MX5XX/6XX/7XX REGISTER 25-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALGNERRCNT<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 25-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 SOFT RESET SIM RESET — — RESET RMCS RESET RFUN RESET TMCS RESET TFUN U-0
PIC32MX5XX/6XX/7XX REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 25/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — EXCESS DFR BPNOBK OFF NOBK OFF — — LONGPRE PUREPRE R/W-1 R/W-0 R/W-
PIC32MX5XX/6XX/7XX REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER (CONTINUED) bit 6 VLANPAD: VLAN Pad Enable bit(1,2) 1 = The MAC will pad all short frames to 64 bytes and append a valid CRC 0 = The MAC does not perform padding of short frames bit 5 PADENABLE: Pad/CRC Enable bit(1,3) 1 = The MAC will pad all short frames 0 = The frames presented to the MAC have a valid length bit 4 CRCENABLE: CRC Enable1 bit 1 = The MAC will append a CRC to every frame whether padding was r
PIC32MX5XX/6XX/7XX REGISTER 25-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 25-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 — U-0 NB2BIPKTGP1
PIC32MX5XX/6XX/7XX REGISTER 25-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY LIMIT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U-0 U-0 U-0 U-0 CWINDOW<5:0> — — — —
PIC32MX5XX/6XX/7XX REGISTER 25-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 MACMAXF<15:8>(1) R/W-1 R/W-1 R/W-1 R/W-0 R/W-
PIC32MX5XX/6XX/7XX REGISTER 25-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit Bit 26/18/10/2 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — — — — RESETRMII(1) — — SPEEDRMII(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — —
PIC32MX5XX/6XX/7XX REGISTER 25-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TESTBP TESTPAUSE(1)
PIC32MX5XX/6XX/7XX REGISTER 25-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT CONFIGURATION REGISTER Bit Range Bit 31/23/15/7 U-0 31:24 23:16 15:8 Bit Bit 30/22/14/6 29/21/13/5 U-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 RESETMGMT — — — — — — — U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 25-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — —
PIC32MX5XX/6XX/7XX REGISTER 25-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PHYADDR<4:0> R/
PIC32MX5XX/6XX/7XX REGISTER 25-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MWTD<15:8> R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 25-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — —
PIC32MX5XX/6XX/7XX REGISTER 25-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — R/W-P R/W-P R/W-P R/W-P — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR6<7:0> R/W-P R/W-P STNAD
PIC32MX5XX/6XX/7XX REGISTER 25-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR4<7:0> R/W-P R/W-P STNA
PIC32MX5XX/6XX/7XX REGISTER 25-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — R/W-P R/W-P R/W-P R/W-P — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR2<7:0> R/W-P R/W-P STNADDR
PIC32MX5XX/6XX/7XX 26.0 Note: COMPARATOR The Comparator module contains two comparators that can be configured in a variety of ways. This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Comparator” (DS60001110) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
Control Registers A000 CM1CON A010 CM2CON A060 CMSTAT Legend: Note 1: COMPARATOR REGISTER MAP 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — ON — COE — CPOL — — — — — — — — — COUT — ON — COE — CPOL — — — — — — — — — COUT — — — — — SIDL — — — — — — — — — — 23/7 22/6 21/5 20/4 19/3 18/2 — — EVPOL<1:0> — — — CREF — — — — — — CCH<1:0> 0000 00C3 — — EVPOL<1:0> — — — CREF — — — — — — CCH<1:0> 0000 00C3 — — — — — — — — —
PIC32MX5XX/6XX/7XX REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 CMxCON: COMPARATOR ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — R/W-0 (1) R/W-0 ON COE R/W-1 R/W-1 EVPOL<1:0> Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 — R/W-0 (2) CPOL Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 R-0 COUT — — —
PIC32MX5XX/6XX/7XX REGISTER 26-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 — — R/W-0 U-0 U-0 U-0 U-0 U-0 SIDL — — — — — U-0 U-0 — — U-0 U-0 U-0 U-0 R-0 R-0 — — — — C2OUT C1OUT Legend: R = Read
PIC32MX5XX/6XX/7XX 27.0 Note: COMPARATOR VOLTAGE REFERENCE (CVREF) A block diagram of the module is illustrated in Figure 27-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output.
Control Register Virtual Address (BF80_#) TABLE 27-1: Legend: 1: 2: 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 — — — — — — — — — — — CVROE — — — — VREFSEL(2) BGSEL<1:0>(2) x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MX5XX/6XX/7XX REGISTER 27-1: Bit Range 31:24 23:16 15:8 7:0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — VREFSEL(2) R/W-1 (2) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CVROE CVRR C
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 330 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 28.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “Power-Saving Features” (DS60001130) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). This section describes power-saving features for the PIC32MX5XX/6XX/7XX family of devices.
PIC32MX5XX/6XX/7XX The processor will exit, or ‘wake-up’, from Sleep mode on one of the following events: • On any interrupt from an enabled source that is operating in Sleep mode. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset • On a WDT time-out If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. 28.3.
PIC32MX5XX/6XX/7XX 29.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 33. “Programming and Diagnostics” (DS60001129) in the “PIC32 Family Reference Manual”, which are available from the Microchip web site (www.microchip.com/PIC32).
2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — — — FCANIO FETHIO FMIIEN — — — — — FSRSSEL<2:0> — — — — FPLLODIV<2:0> xxxx — FPLLIDIV<2:0> xxxx 31:16 FVBUSONIO FUSBIDIO 15:0 18/2 17/1 16/0 xxxx USERID<15:0> 31:16 — — — — — 15:0 UPLLEN — — — — 31:16 — — — — — — 15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC 31:16 — — — — — — — — 15:0 — CP PWP<3:0> — — — — UPLLIDIV<2:0> — xxxx —
PIC32MX5XX/6XX/7XX REGISTER 29-1: Bit Range DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 31/23/15/7 31:24 23:16 15:8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 26/18/10/2 Bit 25/17/9/1 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P — — CP — — — BWP r-1 r-1 r-1 r-1 R/P R/P R/P R/P r-1 r-1 r-1 r-1 — — — — R/P R/P — — — — R/P R/P R/P R/P PWP<7:4> r-1 r-1 r-1 r-1 R/P r-1 — — — — ICESEL — DEBUG<1:0> Legend: r = Reserved bit P = Programmable bit R = Readable b
PIC32MX5XX/6XX/7XX REGISTER 29-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used bit 2 Reserved: Write ‘1’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled) 11 = Debugger is disabled 10 = Debugger is enabled 01 = Reserved (same as ‘11’ setting) 00 = Reserved (same as ‘11’ setting) DS60001156J-page 336 2009-2016 Microc
PIC32MX5XX/6XX/7XX REGISTER 29-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P r-1 r-1 R/P R/P R/P R/P R/P R/P r-1 R/P R/P R/P FWDTEN — — R/P R/P R/P FCKSM<1:0> WDTPS<4:0> — OSCIOFNC R/P r-1 R/P FPBDIV<1:0> r-1 r-1 R/P IESO — FSOSCEN — — POSCMOD<1:0> R/P R/P
PIC32MX5XX/6XX/7XX REGISTER 29-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write ‘1’ bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output is disabled 0 = CLKO output signal is active on the OSCO pin; the Primary Oscillator must be disabled or configured for Externa
PIC32MX5XX/6XX/7XX REGISTER 29-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 R/P R/P R/P — — — — — R/P r-1 r-1 r-1 r-1 UPLLEN — — — — r-1 R/P-1 R/P R/P-1 r-1 — FPLLMUL<2:0> FPLLODIV<2:0> R/P R/P R/P UPLLIDIV<2:0> R/P — R/P R/P FPLLIDIV<2:
PIC32MX5XX/6XX/7XX REGISTER 29-3: bit 2-0 DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider DS60001156J-page 340 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX REGISTER 29-4: Bit Range 31:24 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 R/P R/P FVBUSONIO FUSBIDIO 23:16 15:8 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 R/P R/P R/P — — — FCANIO(1) FETHIO(2) FMIIEN(2) R/P R/P R/P r-1 r-1 r-1 r-1 r-1 — — — — — R/P R/P R/P R/P R/P FSRSSEL<2:0> R/P R/P R/P R/P R/P R/P USERID<15:8> R/P 7:0 R/P R/P R/P R/P USERID<7:0> Lege
PIC32MX5XX/6XX/7XX REGISTER 29-5: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R R Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R R R R R R R (1) VER<3:0> R Bit 24/16/8/0 R (1) R R R R R (1) R R R R R R R (1) R Bit 25/17/9/1 DEVID<27:24> DEVID<23:16> R R R R R R R DEVID<15:8> R DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ =
PIC32MX5XX/6XX/7XX 29.2 On-Chip Voltage Regulator All PIC32MX5XX/6XX/7XX devices’ core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX5XX/6XX/7XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 29-1). This helps to maintain the stability of the regulator.
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 344 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 30.0 INSTRUCTION SET The PIC32MX5XX/6XX/7XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. The PIC32 device family does not support the following features: • Core Extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.imgtec.com for more information. 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 346 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 31.0 DEVELOPMENT SUPPORT ® 31.
PIC32MX5XX/6XX/7XX 31.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC32MX5XX/6XX/7XX 31.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC32MX5XX/6XX/7XX 31.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC32MX5XX/6XX/7XX 32.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC32MX5XX/6XX/7XX 32.1 DC Characteristics TABLE 32-1: OPERATING MIPS VS. VOLTAGE Characteristic DC5 DC5b Note 1: Max. Frequency VDD Range (in Volts)(1) Temp. Range (in °C) PIC32MX5XX/6XX/7XX 2.3-3.6V -40°C to +85°C 80 MHz 2.3-3.6V -40°C to +105°C 80 MHz Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.
PIC32MX5XX/6XX/7XX TABLE 32-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Conditions Operating Voltage Supply Voltage 2.3 — 3.6 V — DC10 VDD DC12 VDR RAM Data Retention Voltage(1) 1.75 — — V — DC16 VPOR VDD Start Voltage to Ensure 1.75 — 2.
PIC32MX5XX/6XX/7XX TABLE 32-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. No. Typical(3) Max.
PIC32MX5XX/6XX/7XX TABLE 32-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. No. Typical(3) Max.
PIC32MX5XX/6XX/7XX TABLE 32-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE)(1,3) for PIC32MX575/675/695/775/795 Family Devices DC30 4.5 6.
PIC32MX5XX/6XX/7XX TABLE 32-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE)(1) for PIC32MX534/564/664/764 Family Devices DC30a 1.5 5 DC30c 3.
PIC32MX5XX/6XX/7XX TABLE 32-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 32-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Characteristics Min. Typical(1) Max. Units DI15 DI16 DI17 DI18 Input Low Voltage I/O Pins: with TTL Buffer with Schmitt Trigger Buffer MCLR(2) OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx VSS VSS VSS VSS VSS VSS — — — — — — 0.
PIC32MX5XX/6XX/7XX TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. IIL Characteristics Min. Typical(1) Max.
PIC32MX5XX/6XX/7XX TABLE 32-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param.
PIC32MX5XX/6XX/7XX TABLE 32-11: DC CHARACTERISTICS: PROGRAM MEMORY(3) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Param. Symbol No. Min. Typ.(1) Max. Units Conditions — E/W — D130 Characteristics EP Cell Endurance 1000 — D130a EP Cell Endurance 20,000 — — E/W D131 VPR VDD for Read 2.3 — 3.6 V D132 See Note 5 — VPEW VDD for Erase or Write 3.
PIC32MX5XX/6XX/7XX TABLE 32-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 3): 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Comments D300 VIOFF Input Offset Voltage — ±7.
PIC32MX5XX/6XX/7XX TABLE 32-14: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics D312 TSET D313 DACREFH CVREF Input Voltage Reference Range D314 DVREF D315 Internal 4-bit DAC Comparator Reference Settling time. DACACC Absolute Accuracy(2) Note 1: 2: Typical Max.
PIC32MX5XX/6XX/7XX 32.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX5XX/6XX/7XX AC characteristics and timing parameters.
PIC32MX5XX/6XX/7XX TABLE 32-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. OS10 FOSC OS11 Min. Typical(1) Max.
PIC32MX5XX/6XX/7XX TABLE 32-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 3.
PIC32MX5XX/6XX/7XX TABLE 32-20: INTERNAL RC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Characteristics Min. Typical Max. Units Conditions -15 — +15 % — LPRC @ 31.25 kHz(1) F21 LPRC Note 1: Change of LPRC frequency as VDD changes.
PIC32MX5XX/6XX/7XX FIGURE 32-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be
PIC32MX5XX/6XX/7XX FIGURE 32-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 32-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 32-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 32-1 for load conditions. TABLE 32-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No.
PIC32MX5XX/6XX/7XX TABLE 32-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns — ns TB11 TTXL TxCK Synchronous, with Low Time prescaler [(12.
PIC32MX5XX/6XX/7XX FIGURE 32-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 32-1 for load conditions. TABLE 32-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [(12.
PIC32MX5XX/6XX/7XX FIGURE 32-9: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure 32-1 for load conditions. TABLE 32-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param No.
PIC32MX5XX/6XX/7XX FIGURE 32-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 32-1 for load conditions. TABLE 32-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 32-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX Bit 14 - - - -1 MSb In SP40 LSb In SP41 Note: Refer to Figure 32-1 for load conditions. TABLE 32-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 32-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 32-1 for load conditions. TABLE 32-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 32-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 32-1 for load conditions. TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max.
PIC32MX5XX/6XX/7XX FIGURE 32-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 32-1 for load conditions. FIGURE 32-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 32-1 for load conditions. 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 32-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. IM10 Symbol TLO:SCL THI:SCL IM11 Min.(1) Max.
PIC32MX5XX/6XX/7XX FIGURE 32-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 32-1 for load conditions. FIGURE 32-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 32-1 for load conditions. 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 32-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No.
PIC32MX5XX/6XX/7XX FIGURE 32-18: CiTx Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 32-34: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param No.
PIC32MX5XX/6XX/7XX TABLE 32-35: ETHERNET MODULE SPECIFICATIONS Standard Operating Conditions (see Note 1): 2.9V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Characteristic Min. Typical Max.
PIC32MX5XX/6XX/7XX FIGURE 32-21: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN VILMAX TX Clock VIHMIN ETXD<3:0>, ETEN, ETXERR FIGURE 32-22: VILMAX ET7 RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN RX Clock VILMAX VIHMIN ERXD<3:0>, ERXDV, ERXERR VILMAX (Setup) ET10 ET10 (Hold) 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 32-36: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Min. Typical Max. Units Greater of VDD – 0.3 or 2.5 — Lesser of VDD + 0.3 or 3.6 V VSS — VSS + 0.
PIC32MX5XX/6XX/7XX TABLE 32-36: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Min. Typical Max. Units Conditions ADC Accuracy – Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.
PIC32MX5XX/6XX/7XX TABLE 32-37: 10-BIT ADC CONVERSION RATE PARAMETERS Standard Operating Conditions (see Note 3): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp ADC Speed(2) 1 Msps to 400 ksps(1) TAD Minimum 65 ns Sampling RS Time Maximum Minimum 132 ns 500 VDD ADC Channels Configuration 3.0V to 3.6V VREF- VREF+ ANx CHX S&H Up to 400 ksps 200 ns 200 ns 5.0 k ADC 2.5V to 3.
PIC32MX5XX/6XX/7XX TABLE 32-38: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions (see Note 4): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max.
PIC32MX5XX/6XX/7XX FIGURE 32-23: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX5XX/6XX/7XX FIGURE 32-24: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP TSAMP AD55 TCONV AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX5XX/6XX/7XX FIGURE 32-25: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 32-39: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Characteristics(1) Symbol Min. Typical Max.
PIC32MX5XX/6XX/7XX FIGURE 32-26: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 32-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX5XX/6XX/7XX FIGURE 32-27: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 32-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX5XX/6XX/7XX TABLE 32-42: USB OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) USB313 VUSB3V3 USB Voltage Min. Typical Max. Units Conditions 3.0 — 3.6 V Voltage on VUSB3V3 must be in this range for proper USB operation — USB315 VILUSB Input Low Voltage for USB Buffer — — 0.
PIC32MX5XX/6XX/7XX FIGURE 32-28: EJTAG TIMING CHARACTERISTICS TTCKcyc TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TTRST*low TTDOout TTDOzstate TRST* Defined Undefined Trf TABLE 32-43: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max.
DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 33-1: VOH – 4x DRIVER PINS FIGURE 33-3: -0.045 0.
PIC32MX5XX/6XX/7XX NOTES: DS60001156J-page 400 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 34.0 PACKAGING INFORMATION 34.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX575F 512H-80I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC32MX5XX/6XX/7XX 34.1 Package Marking Information (Continued) 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX575F 512H-80I/MR e3 0510017 121-Lead TFBGA (10x10x1.1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: DS60001156J-page 402 Example PIC32MX575F 512H-80I/BG e3 0510017 124-Lead VTLA (9x9x0.
PIC32MX5XX/6XX/7XX 34.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D NOTE 2 A B E1/2 E1 A E A SEE DETAIL 1 N 4X N/4 TIPS 0.20 C A-B D 1 3 2 4X NOTE 1 0.20 H A-B D TOP VIEW A2 A 0.05 C SEATING PLANE 0.08 C 64 X b 0.
PIC32MX5XX/6XX/7XX 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2016 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2016 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156J-page 410 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156J-page 412 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) 10x10x1.10 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B NOTE 1 E (DATUM B) (DATUM A) 2X 0.10 C 2X 0.10 C TOP VIEW A DETAIL A A1 SIDE VIEW D1 e DETAIL B L K J H G F E D C B A E1 e BOTTOM VIEW Microchip Technology Drawing C04-148 Rev F Sheet 1 of 2 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) 10x10x1.10 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C 0.10 C DETAIL A NX Øb 0.15 0.08 C A B C DETAIL B Number of Contacts Contact Pitch Overall Height Ball Height Overall Width Array Width Overall Length Array Length Contact Diameter Units Dimension Limits N e A A1 E E1 D D1 b MIN 1.00 0.25 0.
PIC32MX5XX/6XX/7XX 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX DS60001156J-page 416 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC32MX5XX/6XX/7XX APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below.
PIC32MX5XX/6XX/7XX APPENDIX B: REVISION HISTORY Revision A (August 2009) This is the initial released version of this document. Revision B (November 2009) The revision includes the following global update: Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. Other major changes are referenced by their respective chapter/section in Table B-1.
PIC32MX5XX/6XX/7XX TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.0 “Memory Organization” Update Description Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-4 to include the PIC32MX575F256L device. Updated the title of Figure 4-6 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device.
PIC32MX5XX/6XX/7XX Revision C (February 2010) The revision includes the following updates, as described in Table B-2: TABLE B-2: MAJOR SECTION UPDATES Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Update Description Added the following devices: • PIC32MX675F256H • PIC32MX775F256H • PIC32MX775F512H • PIC32MX675F256L • PIC32MX775F256L • PIC32MX775F512L Added the following pins: • EREFCLK • ECRSDV • AEREFCLK • AECRSDV 1.
PIC32MX5XX/6XX/7XX Revision D (May 2010) The revision includes the following updates, as described in Table B-3: TABLE B-3: MAJOR SECTION UPDATES Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Update Description Updated the initial Flash memory range to 64K. Updated the initial SRAM memory range to 16K. Added the following devices (see Table 1, Table 2, Table 3 and the Pin Diagrams): • • • • • • • • • • • • 4.
PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.
PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description 1.0 “Electrical Characteristics” Updated the Typical and Maximum DC Characteristics: Operating Current (IDD) in Table 1-5. Updated the Typical and Maximum DC Characteristics: Idle Current (IIDLE) in Table 1-6. Updated the Typical and Maximum DC Characteristics: Power-Down Current (IPD) in Table 1-7. Added DC Characteristics: Program Memory parameters D130a and D132a in Table 1-11.
PIC32MX5XX/6XX/7XX Revision E (July 2010) Revision F (December 2010) Minor corrections were incorporated throughout the document.
PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 4.0 “Memory Organization” (Continued) 2009-2016 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 7.0 “Interrupt Controller” 1.0 “Oscillator Configuration” 1.0 “Output Compare” 1.0 “Ethernet Controller” 1.0 “Comparator Voltage Reference (CVREF)” 1.0 “Special Features” 1.
PIC32MX5XX/6XX/7XX Revision G (May 2011) The revision includes the following global updates: • All references to VDDCORE/VCAP have been changed to: VCORE/VCAP • Added references to the new V-Temp temperature range: -40ºC to +105ºC TABLE B-5: This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in Table B-5.
PIC32MX5XX/6XX/7XX Revision H (March 2013) This revision includes the following global updates: • Where applicable, control register tables have been added to the document • All references to VCORE were removed • All occurrences of XBGA have been updated to: TFBGA TABLE B-6: • All occurrences of VUSB have been updated to: VUSB3V3 This revision also includes minor typographical and formatting changes throughout the data sheet text.
PIC32MX5XX/6XX/7XX Revision J (September 2016) This revision includes typographical and formatting updates throughout the data sheet text. In addition, all SFR Register maps were moved from the Memory chapter to their respective peripheral chapters. All other major updates are referenced by their respective section in Table B-7. TABLE B-7: MAJOR SECTION UPDATES Section Name Update Description “32-bit Microcontrollers (up to 512 Updated Communication Interfaces for LIN support to 2.1.
PIC32MX5XX/6XX/7XX TABLE B-7: MAJOR SECTION UPDATES (CONTINUED) Section Name 32.0 “Electrical Characteristics” Update Description Note 4 in the Operating Current specification was updated (see Table 32-5). Note 3 in the Idle Current specification was updated (see Table 32-6). Note 6 references in the Power-Down Current specification were updated (see Table 32-7). The Program Memory parameters, D135, D136, and D137, and Note 4 were updated (see Table 32-11).
PIC32MX5XX/6XX/7XX INDEX A AC Characteristics ............................................................ 366 10-bit Conversion Rate Parameters.......................... 390 ADC Specifications ................................................... 388 Analog-to-Digital Conversion Requirements............. 391 EJTAG Timing Requirements ................................... 398 Ethernet .................................................................... 386 Internal FRC Accuracy..................................
PIC32MX5XX/6XX/7XX Oscillator Configuration....................................................... 95 Output Compare................................................................ 185 P Packaging ......................................................................... 401 Details ....................................................................... 403 Marking ..................................................................... 401 Parallel Master Port (PMP) ...........................................
PIC32MX5XX/6XX/7XX EMAC1SA0 (Ethernet Controller MAC Station Address 0)....................................................................... 320 EMAC1SA1 (Ethernet Controller MAC Station Address 1)....................................................................... 321 EMAC1SA2 (Ethernet Controller MAC Station Address 2)....................................................................... 322 EMAC1SUPP (Ethernet Controller MAC PHY Support) . 313 EMAC1TEST (Ethernet Controller MAC Test) ..........
PIC32MX5XX/6XX/7XX SPIx Slave Mode (CKE = 1)...................................... 379 Timer1, 2, 3, 4, 5 External Clock............................... 372 UART Reception ....................................................... 204 UART Transmission (8-bit or 9-bit Data)................... 204 Timing Requirements CLKO and I/O ........................................................... 369 Timing Specifications CAN I/O Requirements .............................................
PIC32MX5XX/6XX/7XX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC32MX5XX/6XX/7XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Example: PIC32MX575F256H-80I/PT: General purpose PIC32, 32-bit RISC MCU, 256 KB program memory, 64-pin, Industrial temperature, TQFP package.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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