Datasheet

 2011-2017 Microchip Technology Inc. DS30009995E-page 48
PIC24FV32KA304 FAMILY
TABLE 4-17: CTMU REGISTER MAP
File
Name
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CTMUCON1 035A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000
CTMUCON2 035C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2EMOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — 0000
CTMUICON 035E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000
AD1CTMUENH 0360 — — — — — — — — — — — — — — CTMEN<17:16> 0000
AD1CTMUENL 0362 CTMEN<15:0> 0000
Legend: — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.
TABLE 4-18: ANALOG SELECT REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
ANSA 04E0
— — — — — — — — — — — —ANSA<3:0>000F
ANSB 04E2 ANSB<15:12>
— — — — — — — ANSB<4:0>
(1)
F01F
ANSC 04E4
— — — — — — — — — — — — — ANSC<2:0>
(1,2)
0007
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: ANSB3 and ANSC<2:0> bits are not implemented in 20-pin devices.
2: These bits are not implemented in 28-pin devices.
TABLE 4-19: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
ALRMVAL 0620 ALRMVAL xxxx
ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL 0624 RTCVAL xxxx
RCFGCAL 0626 RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000
RTCPWC 0628 PWCEN PWCPOL PWCCPRE PWCSPRE RTCCLK1 RTCCLK0 RTCOUT1 RTCOUT0
— — — — — — — — xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: TRIPLE COMPARATOR REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CMSTAT 0630 CMIDL
— — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT xxxx
CVRCON 0632
— — — — — — — — CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000
CM1CON 0634 CON COE CPOL CLPWR
— — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 xxxx
CM2CON 0636 CON COE CPOL CLPWR
— — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM3CON 0638 CON COE CPOL CLPWR
— — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.