Datasheet
Table Of Contents
- Power Management Modes
- High-Performance CPU
- Peripheral Features
- Analog Features
- Special Microcontroller Features
- Pin Diagrams
- Pin Diagrams
- Pin Diagrams
- Pin Diagrams
- Pin Diagrams
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers
- 3.0 CPU
- 4.0 Memory Organization
- 4.1 Program Address Space
- 4.2 Data Address Space
- 4.2.1 Data Space Width
- 4.2.2 Data Memory Organization and Alignment
- 4.2.3 Near Data Space
- 4.2.4 SFR Space
- TABLE 4-2: Implemented Regions of SFR Data Space
- TABLE 4-3: CPU Core Registers Map
- TABLE 4-4: ICN Register Map
- TABLE 4-5: Interrupt Controller Register Map
- TABLE 4-6: Timer Register Map
- TABLE 4-7: Input Capture Register Map
- TABLE 4-8: Output Compare Register Map
- TABLE 4-9: I2Cx Register Map
- TABLE 4-10: UARTx Register Map
- TABLE 4-11: SPIx Register Map
- TABLE 4-12: PORTA Register Map
- TABLE 4-13: PORTB Register Map
- TABLE 4-14: PORTC Register Map(1)
- TABLE 4-15: Pad Configuration Register Map
- TABLE 4-16: A/D Register Map
- TABLE 4-17: CTMU Register Map
- TABLE 4-18: Analog Select Register Map
- TABLE 4-19: Real-Time Clock and Calendar Register Map
- TABLE 4-20: Triple Comparator Register Map
- TABLE 4-21: CRC Register Map
- TABLE 4-22: Clock Control Register Map
- TABLE 4-23: Deep Sleep Register Map
- TABLE 4-24: NVM Register Map
- TABLE 4-25: Ultra Low-Power Wake-up Register Map
- TABLE 4-26: PMD Register Map
- 4.2.5 Software Stack
- 4.3 Interfacing Program and Data Memory Spaces
- 5.0 Flash Program Memory
- 5.1 Table Instructions and Flash Programming
- 5.2 RTSP Operation
- 5.3 Enhanced In-Circuit Serial Programming
- 5.4 Control Registers
- 5.5 Programming Operations
- Register 5-1: NVMCON: Flash Memory Control Register
- 5.5.1 Programming Algorithm for Flash Program Memory
- EXAMPLE 5-1: Erasing a Program Memory Row – Assembly Language Code
- EXAMPLE 5-2: Erasing a Program Memory Row – ‘C’ Language Code
- EXAMPLE 5-3: Loading the Write Buffers – Assembly Language Code
- EXAMPLE 5-4: Loading the Write Buffers – ‘C’ Language Code
- EXAMPLE 5-5: Initiating a Programming Sequence – Assembly Language Code
- EXAMPLE 5-6: Initiating a Programming Sequence – ‘C’ Language Code
- 6.0 Data EEPROM Memory
- 7.0 Resets
- 8.0 Interrupt Controller
- 8.1 Interrupt Vector Table (IVT)
- 8.2 Reset Sequence
- 8.3 Interrupt Control and Status Registers
- Register 8-1: SR: ALU STATUS Register
- Register 8-2: CORCON: CPU Control Register
- Register 8-3: INTCON1: Interrupt Control Register 1
- Register 8-4: INTCON2: Interrupt Control Register2
- Register 8-5: IFS0: Interrupt Flag Status Register 0
- Register 8-6: IFS1: Interrupt Flag Status Register 1
- Register 8-7: IFS2: Interrupt Flag Status Register 2
- Register 8-8: IFS3: Interrupt Flag Status Register 3
- Register 8-9: IFS4: Interrupt Flag Status Register 4
- Register 8-10: IFS5: Interrupt Flag Status Register 5
- Register 8-11: IEC0: Interrupt Enable Control Register 0
- Register 8-12: IEC1: Interrupt Enable Control Register 1
- Register 8-13: IEC2: Interrupt Enable Control Register 2
- Register 8-14: IEC3: Interrupt Enable Control Register 3
- Register 8-15: IEC4: Interrupt Enable Control Register 4
- Register 8-16: IEC5: Interrupt Enable Control Register 5
- Register 8-17: IPC0: Interrupt Priority Control Register 0
- Register 8-18: IPC1: Interrupt Priority Control Register 1
- Register 8-19: IPC2: Interrupt Priority Control Register 2
- Register 8-20: IPC3: Interrupt Priority Control Register 3
- Register 8-21: IPC4: Interrupt Priority Control Register 4
- Register 8-22: IPC5: Interrupt Priority Control Register 5
- Register 8-23: IPC6: Interrupt Priority Control Register 6
- Register 8-24: IPC7: Interrupt Priority Control Register 7
- Register 8-25: IPC8: Interrupt Priority Control Register 8
- Register 8-26: IPC9: Interrupt Priority Control Register 9
- Register 8-27: IPC12: Interrupt Priority Control Register 12
- Register 8-28: IPC15: Interrupt Priority Control Register 15
- Register 8-29: IPC16: Interrupt Priority Control Register 16
- Register 8-30: IPC18: Interrupt Priority Control Register 18
- Register 8-31: IPC19: Interrupt Priority Control Register 19
- Register 8-32: IPC20: Interrupt Priority Control Register 20
- Register 8-33: INTTREG: Interrupt Control and Status Register
- 8.4 Interrupt Setup Procedures
- 9.0 Oscillator Configuration
- 10.0 Power-Saving Features
- 11.0 I/O Ports
- 12.0 Timer1
- 13.0 Timer2/3 and Timer4/5
- FIGURE 13-1: Timer2/3 and Timer4/5 (32-Bit) Block Diagram
- FIGURE 13-2: Timer2 and Timer4 (16-Bit Synchronous) Block Diagram
- FIGURE 13-3: Timer3 and Timer5 (16-Bit Asynchronous) Block Diagram
- Register 13-1: TxCON: Timer2 and Timer4 Control Register
- Register 13-2: TyCON: Timer3 and Timer5 Control Register
- 14.0 Input Capture with Dedicated Timers
- 15.0 Output Compare with Dedicated Timers
- 16.0 Serial Peripheral Interface (SPI)
- FIGURE 16-1: SPI1 Module Block Diagram (Standard Buffer Mode)
- FIGURE 16-2: SPI1 Module Block Diagram (Enhanced Buffer Mode)
- Register 16-1: SPIxSTAT: SPIx Status and Control Register
- Register 16-2: SPIxCON1: SPIx Control Register 1
- Register 16-3: SPIxCON2: SPIx Control Register 2
- EQUATION 16-1: Relationship Between Device and SPIx Clock Speed(1)
- TABLE 16-1: Sample SCKx Frequencies(1,2)
- 17.0 Inter-Integrated Circuit (I2C)
- 18.0 Universal Asynchronous Receiver Transmitter (UART)
- 19.0 Real-Time Clock and Calendar (RTCC)
- 20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
- 21.0 High/Low-Voltage Detect (HLVD)
- 22.0 12-Bit A/D Converter with Threshold Detect
- FIGURE 22-1: 12-Bit A/D Converter Block Diagram
- 22.1 A/D Control Registers
- 22.1.1 Control Registers
- 22.1.2 A/D Result Buffers
- Register 22-1: AD1CON1: A/D Control Register 1
- Register 22-2: AD1CON2: A/D Control Register 2
- Register 22-3: AD1CON3: A/D Control Register 3
- Register 22-4: AD1CON5: A/D Control Register 5
- Register 22-5: AD1CHS: A/D Sample Select Register
- Register 22-6: AD1CHITH: A/D Scan Compare Hit Register (High Word)(1)
- Register 22-7: AD1CHITL: A/D Scan Compare Hit Register (Low Word)(1)
- Register 22-8: AD1CSSH: A/D Input Scan Select Register (High Word)(1)
- Register 22-9: AD1CSSL: A/D Input Scan Select Register (Low Word)(1)
- Register 22-10: AD1CTMUENH: A/D CTMU Enable Register (High Word)(1)
- Register 22-11: AD1CTMUENL: A/D CTMU Enable Register (Low Word)(1)
- 22.2 A/D Sampling Requirements
- 22.3 Transfer Function
- 22.4 Buffer Data Formats
- FIGURE 22-4: A/D Output Data Formats (12-Bit)
- TABLE 22-1: Numerical Equivalents of Various Result Codes: 12-Bit Integer Formats
- TABLE 22-2: Numerical Equivalents of Various Result Codes: 12-Bit Fractional Formats
- FIGURE 22-5: A/D Output Data Formats (10-Bit)
- TABLE 22-3: Numerical Equivalents of Various Result Codes: 10-Bit Integer Formats
- TABLE 22-4: Numerical Equivalents of Various Result Codes: 10-Bit Fractional Formats
- 23.0 Comparator Module
- 24.0 Comparator Voltage Reference
- 25.0 Charge Time Measurement Unit (CTMU)
- 26.0 Special Features
- 26.1 Configuration Bits
- TABLE 26-1: Configuration Registers Locations
- Register 26-1: FBS: Boot Segment Configuration Register
- Register 26-2: FGS: General Segment Configuration Register
- Register 26-3: FOSCSEL: Oscillator Selection Configuration Register
- Register 26-4: FOSC: Oscillator Configuration Register
- Register 26-5: FWDT: Watchdog Timer Configuration Register
- Register 26-6: FPOR: Reset Configuration Register
- Register 26-7: FICD: In-Circuit Debugger Configuration Register
- Register 26-8: FDS: Deep Sleep Configuration Register
- Register 26-9: DEVID: Device ID Register
- Register 26-10: DEVREV: Device Revision Register
- 26.2 On-Chip Voltage Regulator
- 26.3 Watchdog Timer (WDT)
- 26.4 Deep Sleep Watchdog Timer (DSWDT)
- 26.5 Program Verification and Code Protection
- 26.6 In-Circuit Serial Programming
- 26.7 In-Circuit Debugger
- 26.1 Configuration Bits
- 27.0 Development Support
- 27.1 MPLAB X Integrated Development Environment Software
- 27.2 MPLAB XC Compilers
- 27.3 MPASM Assembler
- 27.4 MPLINK Object Linker/ MPLIB Object Librarian
- 27.5 MPLAB Assembler, Linker and Librarian for Various Device Families
- 27.6 MPLAB X SIM Software Simulator
- 27.7 MPLAB REAL ICE In-Circuit Emulator System
- 27.8 MPLAB ICD 3 In-Circuit Debugger System
- 27.9 PICkit 3 In-Circuit Debugger/ Programmer
- 27.10 MPLAB PM3 Device Programmer
- 27.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits
- 27.12 Third-Party Development Tools
- 28.0 Instruction Set Summary
- 29.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 29.1 DC Characteristics
- FIGURE 29-1: PIC24FV32KA304 Voltage-Frequency Graph (Industrial and Extended)
- FIGURE 29-2: PIC24F32KA304 Family Voltage-Frequency Graph (Industrial and Extended)
- TABLE 29-1: Thermal Operating Conditions
- TABLE 29-2: Thermal Packaging Characteristics
- TABLE 29-3: DC Characteristics: Temperature and Voltage Specifications
- TABLE 29-4: High/Low–Voltage Detect Characteristics
- TABLE 29-5: BOR Trip Points
- TABLE 29-6: DC Characteristics: Operating Current (Idd)
- TABLE 29-7: DC Characteristics: Idle Current (Iidle)
- TABLE 29-8: DC Characteristics: Power-Down Current (Ipd)
- TABLE 29-9: DC Characteristics: I/O Pin Input Specifications
- TABLE 29-10: DC Characteristics: I/O Pin Output Specifications
- TABLE 29-11: DC Characteristics: Program Memory
- TABLE 29-12: DC Characteristics: Data EEPROM Memory
- TABLE 29-13: DC Characteristics: Comparator Specifications
- TABLE 29-14: DC Characteristics: Comparator Voltage Reference Specifications
- TABLE 29-15: Internal Voltage Regulator Specifications
- TABLE 29-16: CTMU Current Source Specifications
- 29.2 AC Characteristics and Timing Parameters
- TABLE 29-17: Temperature and Voltage Specifications – AC
- FIGURE 29-3: Load Conditions for Device Timing Specifications
- TABLE 29-18: Capacitive Loading Requirements on Output Pins
- FIGURE 29-4: External Clock Timing
- TABLE 29-19: External Clock Timing Requirements
- TABLE 29-20: PLL Clock Timing Specifications
- TABLE 29-21: AC Characteristics: Internal RC Accuracy
- TABLE 29-22: Internal RC Oscillator Specifications
- FIGURE 29-5: CLKO and I/O Timing Characteristics
- TABLE 29-23: CLKO and I/O Timing Requirements
- TABLE 29-24: Comparator Timings
- TABLE 29-25: Comparator Voltage Reference Settling Time Specifications
- FIGURE 29-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics
- FIGURE 29-7: Brown-out Reset Characteristics
- TABLE 29-26: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-Up Timer, and Brown-Out Reset Timing Requirements
- FIGURE 29-8: Timer1/2/3/4/5 External Clock Input Timing
- TABLE 29-27: Timer1/2/3/4/5 External Clock Input Requirements
- FIGURE 29-9: Input Capture x Timings
- TABLE 29-28: Input Capture x Requirements
- FIGURE 29-10: Output Compare x Timings
- TABLE 29-29: Output Capture Requirements
- FIGURE 29-11: PWM Module Timing Requirements
- TABLE 29-30: PWM Timing Requirements
- FIGURE 29-12: I2C Bus Start/Stop Bits Timing Characteristics (Master Mode)
- TABLE 29-31: I2C Bus Start/Stop Bit Timing Requirements (Master Mode)
- FIGURE 29-13: I2C Bus Data Timing Characteristics (Master Mode)
- TABLE 29-32: I2C Bus Data Timing Requirements (Master Mode)
- FIGURE 29-14: I2C Bus Data Timing Characteristics (Slave Mode)
- TABLE 29-33: I2C Bus Data Timing Requirements (Slave Mode)
- FIGURE 29-15: I2C Bus Start/Stop Bits Timing Characteristics (Slave Mode)
- TABLE 29-34: I2C Bus Start/Stop Bits Timing Requirements (Slave Mode)
- FIGURE 29-16: UARTx Baud Rate Generator Output Timing
- FIGURE 29-17: UARTx Start Bit Edge Detection
- TABLE 29-35: UARTx Timing Requirements
- FIGURE 29-18: SPIx Module Master Mode Timing Characteristics (CKE = 0)
- TABLE 29-36: SPIx Master Mode Timing Requirements (CKE = 0)
- FIGURE 29-19: SPIx Module Master Mode Timing Characteristics (CKE = 1)
- TABLE 29-37: SPIx Module Master Mode Timing Requirements (CKE = 1)
- FIGURE 29-20: SPIx Module Slave Mode Timing Characteristics (CKE = 0)
- TABLE 29-38: SPIx Module Slave Mode Timing Requirements (CKE = 0)
- FIGURE 29-21: SPIx Module Slave Mode Timing Characteristics (CKE = 1)
- TABLE 29-39: SPIx Module Slave Mode Timing Requirements (CKE = 1)
- TABLE 29-40: A/D Module Specifications
- FIGURE 29-22: A/D Conversion Timing
- TABLE 29-41: A/D Conversion Timing Requirements(1)
- 30.0 DC and AC Characteristics Graphs and Tables
- 30.1 Characteristics for Industrial Temperature Devices (-40°C to +85°C)
- FIGURE 30-1: Typical and Maximum Idd vs. Fosc (EC Mode, 2 MHz to 32 MHz, -40°C to +85°C)
- FIGURE 30-2: Typical and Maximum Idd vs. Fosc (EC Mode, 1.95 kHz to 1 MHz, +25°C)
- FIGURE 30-3: Typical and Maximum Iidle vs. Frequency (EC Mode, 2 MHz to 32 MHz)
- FIGURE 30-4: Typical and Maximum Iidle vs. Frequency (EC Mode, 1.95 kHz to 1 MHz)
- FIGURE 30-5: Typical Idd vs. Vdd (8 MHz, EC Mode)
- FIGURE 30-6: Typical Idd vs. Vdd (FRC Mode)
- FIGURE 30-7: Typical and Maximum Idd vs. Temperature (FRC Mode)
- FIGURE 30-8: Typical and Maximum Iidle vs. Vdd (FRC Mode)
- FIGURE 30-9: Typical and Maximum Iidle vs. Temperature (FRC Mode)
- FIGURE 30-10: FRC Frequency Accuracy vs. Vdd
- FIGURE 30-11: FRC Frequency Accuracy vs. Temperature (2.0V £ Vdd £ 5.5V)
- FIGURE 30-12: LPRC Frequency Accuracy vs. Vdd
- FIGURE 30-13: LPRC Frequency Accuracy vs. Temperature (2.0V £ Vdd £ 5.5V)
- FIGURE 30-14: Typical and Maximum Ipd vs. Vdd
- FIGURE 30-15: Typical and Maximum Ipd vs. Temperature
- FIGURE 30-16: Typical and Maximum Ipd vs. Vdd (Deep Sleep Mode)
- FIGURE 30-17: Typical and Maximum Ipd vs. Temperature (Deep Sleep Mode)
- FIGURE 30-18: Typical DIbor vs. Vdd
- FIGURE 30-19: Typical DIwdt vs. Vdd
- FIGURE 30-20: Typical DIdsbor vs. Vdd
- FIGURE 30-21: Typical DIhlvd vs. Vdd
- FIGURE 30-22: Typical DIdswdt vs. Vdd
- FIGURE 30-23: Typical Vbor vs. Temperature (BOR Trip Point 3)
- FIGURE 30-24: Typical Voh vs. Ioh (General Purpose I/O, as a Function of Vdd)
- FIGURE 30-25: Typical Voh vs. Ioh (General Purpose I/O, as a Function of Temperature, 2.0V £ Vdd £ 5.5V)
- FIGURE 30-26: Typical Vol vs. Iol (General Purpose I/O, as a Function of Vdd)
- FIGURE 30-27: Typical Vol vs. Iol (General Purpose I/O, as a Function of Temperature, 2.0V £ Vdd £ 5.5V)
- FIGURE 30-28: Vil/Vih vs. Vdd (General Purpose I/O, Temperatures as Noted)
- FIGURE 30-29: Vil/Vih vs. Vdd (I2C, Temperatures as Noted)
- FIGURE 30-30: Vil/Vih vs. Vdd (OSCO, Temperatures as Noted)
- FIGURE 30-31: Vil/Vih vs. Vdd (MCLR, Temperatures as Noted)
- FIGURE 30-32: Typical Band Gap Voltage vs. Vdd
- FIGURE 30-33: Typical Band Gap Voltage vs. Temperature (2.0V £ Vdd £ 5.5V)
- FIGURE 30-34: Typical Voltage Regulator Output vs. Vdd
- FIGURE 30-35: Typical Voltage Regulator Output vs. Temperature
- FIGURE 30-36: HLVD Trip Point Voltage vs. Temperature (HLVDL<3:0> = 0000, PIC24F32KA304 Family Devices ONLY
- FIGURE 30-37: Temperature Sensor Diode Voltage vs. Temperature (2.0V £ Vdd £ 5.5V)
- FIGURE 30-38: CTMU Output Current vs. Temperature (IRNG<1:0> = 01, 2.0V £ Vdd £ 5.5V)
- FIGURE 30-39: CTMU Output Current vs. Vdd (IRNG<1:0> = 01)
- 30.2 Characteristics for Extended Temperature Devices (-40°C to +125°C)
- FIGURE 30-40: Typical and Maximum Iidle vs. Vdd (FRC Mode)
- FIGURE 30-41: Typical and Maximum Iidle vs. Temperature (FRC Mode)
- FIGURE 30-42: Typical and Maximum Ipd vs. Vdd
- FIGURE 30-43: Typical and Maximum Ipd vs. Temperature
- FIGURE 30-44: Typical and Maximum Ipd vs. Vdd (Deep Sleep Mode)
- FIGURE 30-45: Typical and Maximum Ipd vs. Temperature (Deep Sleep Mode)
- FIGURE 30-46: Typical DIwdt vs. Vdd
- FIGURE 30-47: Typical DIdsbor vs. Vdd
- FIGURE 30-48: Typical DIhlvd vs. Vdd
- FIGURE 30-49: Typical Vol vs. Iol (General I/O, 2.0V £ Vdd £ 5.5V)
- FIGURE 30-50: Typical Voh vs. Ioh (General I/O, as a Function of Temperature, 2.0V £ Vdd £ 5.5V)
- FIGURE 30-51: Vil/Vih vs. Vdd (General Purpose I/O, Temperatures as Noted)
- FIGURE 30-52: Vil/Vih vs. Vdd (I2C, Temperatures as Noted)
- FIGURE 30-53: Vil/Vih vs. Vdd (OSCO, Temperatures as Noted)
- FIGURE 30-54: Vil/Vih vs. Vdd (MCLR, Temperatures as Noted)
- FIGURE 30-55: Typical Band Gap Voltage vs. Temperature (2.0V £ Vdd £ 5.5V)
- FIGURE 30-56: Typical Voltage Regulator Output vs. Temperature
- 30.1 Characteristics for Industrial Temperature Devices (-40°C to +85°C)
- 31.0 Packaging Information
- Appendix A: Revision History
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service

PIC24FV32KA304 FAMILY
DS30009995E-page 41 2011-2017 Microchip Technology Inc.
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP
0000
IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
0000
IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF —OC3IF— — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF
0000
IFS2 0088 — — — — — — — — — —IC3IF— — — SPI2IF SPF2IF
0000
IFS3 008A —RTCIF — — — — — — — — — — — MI2C2IF SI2C2IF —
0000
IFS4 008C — —CTMUIF— — — —HLVDIF— — — — CRCIF U2ERIF U1ERIF —
0000
IFS5 008E — — — — — — — — — — — — — — —ULPWUIF
0000
IEC0 0094 NVMIE — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE
0000
IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE —OC3IE— — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE
0000
IEC2 0098 — — — — — — — — — —IC3IE— — — SPI2IE SPF2IE
0000
IEC3 009A —RTCIE — — — — — — — — — — — MI2C2IE SI2C2IE —
0000
IEC4 009C — —CTMUIE— — — —HLVDIE— — — — CRCIE U2ERIE U1ERIE —
0000
IEC5 009E — — — — — — — — — — — — — — —ULPWUIE
0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0
4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — —
4444
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0
4444
IPC3 00AA — NVMIP2 NVMIP1 NVMIP0 — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0
4044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0
4444
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0
0004
IPC6 00B0 — T4IP2 T4IP1 T4IP0 — — — — — OC3IP2 OC3IP1 OC3IP0 — — — —
4040
IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0
4440
IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0
0044
IPC9 00B6 — — — — — — — — — IC3IP2 IC3IP1 IC3IP0 — — — —
0040
IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — —
0440
IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — —
0400
IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — —
4440
IPC18 00C8 — — — — — — — — — — — — — HLVDIP2 HLVDIP1 HLVDIP0
0004
IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — —
0040
IPC20 00CC — — — — — — — — — — — — — ULPWUIP2 ULPWUIP1 ULPWUIP0
0000
INTTREG 00E0 CPUIRQ —VHOLD— ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.