Datasheet

PIC24FV32KA304 FAMILY
DS30009995E-page 294  2011-2017 Microchip Technology Inc.
FIGURE 29-22: A/D CONVERSION TIMING
TABLE 29-41: A/D CONVERSION TIMING REQUIREMENTS
(1)
AC CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature -40°C  T A  +85°C for Industrial
-40°C
 T A  +125°C for Extended
Param
No.
Symbol Characteristic Min. Typ Max. Units Conditions
Clock Parameters
AD50 T AD A/D Clock Period 600 — — ns T CY = 75 ns, AD1CON3 in
default state
AD51 T
RC A/D Internal RC Oscillator
Period
—1.67 — µs
Conversion Rate
AD55 T CONV Conversion Time —
—
12
14
—
—
T AD
T AD
10-bit results
12-bit results
AD56 F
CNV Throughput Rate — — 100 ksps
AD57 T
SAMP Sample Time — 1 — T AD
AD58 T ACQ Acquisition Time 750 — — ns (Note 2)
AD59 T SWC Switching Time from Convert
to Sample
—— (Note 3)
AD60 T DIS Discharge Time 12 — — T AD
Clock Parameters
AD61 T PSS Sample Start Delay from
Setting Sample bit (SAMP)
2— 3 T AD
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to V SS or V SS to V DD ).
3: On the following cycle of the device clock.
AD55
AD50
AD58
BCLR AD1CON1, SAMP
Q3/Q4
A/D CLK
(1)
A/D DATA
ADC1BUFn
AD1IF
SAMP
OLD DATA
SAMPLING STOPPED
NEW DATA
(Note 2)
11 10 9 2 1 0
Note 1: If the A/D clock source is selected as RC, a time of T CY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
. . .
. . .
T CY
BSET AD1CON1, SAMP
AD59