Datasheet

PIC24FV32KA304 FAMILY
DS30009995E-page 220  2011-2017 Microchip Technology Inc.
22.2 A/D Sampling Requirements
The analog input model of the 12-bit A/D Converter is
shown in Figure 22-2. The total sampling time for the
A/D is a function of the holding capacitor charge time.
For the A/D Converter to meet its specified accuracy, the
Charge Holding Capacitor (C
HOLD ) must be allowed to
fully charge to the voltage level on the analog input pin.
The Source (R
S ) impedance, the Interconnect (R IC )
impedance and the internal Sampling Switch (R
SS )
impedance combine to directly affect the time required to
charge C
HOLD . The combined impedance of the analog
sources must, therefore, be small enough to fully charge
the holding capacitor within the chosen sample time. To
minimize the effects of pin leakage currents on the
accuracy of the A/D Converter, the maximum recom-
mended Source impedance, R
S , is 2.5 k. After the
analog input channel is selected (changed), this
sampling function must be completed prior to starting the
conversion. The internal holding capacitor will be in a
discharged state prior to each sample operation.
At least 1 T
AD time period should be allowed between
conversions for the sample time. For more details, see
Section 29.0 “Electrical Characteristics” .
EQUATION 22-1: A/D CONVERSION CLOCK
PERIOD
FIGURE 22-2: 12-BIT A/D CONVERTER ANALOG INPUT MODEL
Note: Based on T CY = 2/F OSC ; Doze mode
and PLL are disabled.
T
AD = T CY (ADCS + 1)
T AD
T CY
ADCS =
– 1
R SS  3 k
C PIN
Rs
ANx
I
LEAKAGE
R IC  250
Sampling
Switch
R
SS
C HOLD
V SS
= 32 pF
500 nA
Legend: C PIN
V T
I LEAKAGE
R IC
R SS
C HOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the Pin Due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample-and-Hold Capacitance (from DAC)
Various Junctions
Note: The C PIN value depends on the device package and is not tested. The effect of C PIN is negligible if Rs  5 k.
VA