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Table Of Contents

Power Management Modes
High-Performance CPU
Peripheral Features
Analog Features
Special Microcontroller Features
Pin Diagrams
Pin Diagrams
Pin Diagrams
Pin Diagrams
Pin Diagrams
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 Core Features
- 1.2 Other Special Features
- 1.3 Details on Individual Family Members
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers
- 2.1 Basic Connection Requirements
  - FIGURE 2-1: Recommended Minimum Connections
- 2.2 Power Supply Pins
  - 2.2.1 Decoupling Capacitors
  - 2.2.2 Tank Capacitors
- 2.3 Master Clear (MCLR) Pin
  - FIGURE 2-2: Example of MCLR Pin Connections
- 2.4 Voltage Regulator Pin (Vcap)
- 2.5 ICSP Pins
- 2.6 External Oscillator Pins
- 2.7 Unused I/Os
  - FIGURE 2-5: Suggested Placement of the Oscillator Circuit
3.0 CPU
- 3.1 Programmer’s Model
- 3.2 CPU Control Registers
  - Register 3-1: SR: ALU STATUS Register
  - Register 3-2: CORCON: CPU Control Register
- 3.3 Arithmetic Logic Unit (ALU)
4.0 Memory Organization
- 4.1 Program Address Space
- 4.2 Data Address Space
- 4.3 Interfacing Program and Data Memory Spaces
5.0 Flash Program Memory
- 5.1 Table Instructions and Flash Programming
  - FIGURE 5-1: Addressing for Table Registers
- 5.2 RTSP Operation
- 5.3 Enhanced In-Circuit Serial Programming
- 5.4 Control Registers
- 5.5 Programming Operations
  - Register 5-1: NVMCON: Flash Memory Control Register
  - 5.5.1 Programming Algorithm for Flash Program Memory
6.0 Data EEPROM Memory
- 6.1 NVMCON Register
- 6.2 NVMKEY Register
  - EXAMPLE 6-1: Data EEPROM Unlock Sequence
  - Register 6-1: NVMCON: Nonvolatile Memory Control Register
- 6.3 NVM Address Register
  - FIGURE 6-1: Data EEPROM Addressing with TBLPAG and NVM Address Registers
- 6.4 Data EEPROM Operations
7.0 Resets
- FIGURE 7-1: Reset System Block Diagram
- Register 7-1: RCON: Reset Control Register(1)
- TABLE 7-1: Reset Flag Bit Operation
- 7.1 Clock Source Selection at Reset
  - TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)
- 7.2 Device Reset Times
- 7.3 Special Function Register Reset States
- 7.4 Deep Sleep BOR (DSBOR)
- 7.5 Brown-out Reset (BOR)
8.0 Interrupt Controller
- 8.1 Interrupt Vector Table (IVT)
  - 8.1.1 Alternate Interrupt Vector Table (AIVT)
- 8.2 Reset Sequence
- 8.3 Interrupt Control and Status Registers
- 8.4 Interrupt Setup Procedures
9.0 Oscillator Configuration
- FIGURE 9-1: PIC24FV32KA304 Family Clock Diagram
- 9.1 CPU Clocking Scheme
- 9.2 Initial Configuration on POR
  - 9.2.1 Clock Switching Mode Configuration Bits
    - TABLE 9-1: Configuration Bit Values for Clock Selection
- 9.3 Control Registers
- 9.4 Clock Switching Operation
  - 9.4.1 Enabling Clock Switching
  - 9.4.2 Oscillator Switching Sequence
    - EXAMPLE 9-1: Basic Code Sequence for Clock Switching
- 9.5 Reference Clock Output
  - Register 9-4: REFOCON: Reference Oscillator Control Register
10.0 Power-Saving Features
- 10.1 Clock Frequency and Clock Switching
- 10.2 Instruction-Based Power-Saving Modes
- 10.3 Ultra Low-Power Wake-up
- 10.4 Voltage Regulator-Based Power-Saving Features
- 10.5 Doze Mode
- 10.6 Selective Peripheral Module Control
11.0 I/O Ports
- 11.1 Parallel I/O (PIO) Ports
  - FIGURE 11-1: Block Diagram of a Typical Shared Port Structure
  - 11.1.1 Open-Drain Configuration
- 11.2 Configuring Analog Port Pins
  - 11.2.1 Analog Selection Registers
  - 11.2.2 I/O Port Write/Read Timing
- 11.3 Input Change Notification (ICN)
  - EXAMPLE 11-1: Port Write/Read Example
12.0 Timer1
- FIGURE 12-1: 16-Bit Timer1 Module Block Diagram
- Register 12-1: T1CON: Timer1 Control Register
13.0 Timer2/3 and Timer4/5
- FIGURE 13-1: Timer2/3 and Timer4/5 (32-Bit) Block Diagram
- FIGURE 13-2: Timer2 and Timer4 (16-Bit Synchronous) Block Diagram
- FIGURE 13-3: Timer3 and Timer5 (16-Bit Asynchronous) Block Diagram
- Register 13-1: TxCON: Timer2 and Timer4 Control Register
- Register 13-2: TyCON: Timer3 and Timer5 Control Register
14.0 Input Capture with Dedicated Timers
- 14.1 General Operating Modes
  - 14.1.1 Synchronous and Trigger Modes
    - FIGURE 14-1: Input Capture x Block Diagram
  - 14.1.2 Cascaded (32-Bit) Mode
- 14.2 Capture Operations
  - Register 14-1: ICxCON1: Input Capture x Control Register 1
  - Register 14-2: ICxCON2: Input Capture x Control Register 2
15.0 Output Compare with Dedicated Timers
- 15.1 General Operating Modes
  - 15.1.1 Synchronous and Trigger Modes
  - 15.1.2 Cascaded (32-Bit) Mode
    - FIGURE 15-1: Output Compare x Block Diagram (16-Bit Mode)
- 15.2 Compare Operations
- 15.3 Pulse-Width Modulation (PWM) Mode
- 15.4 Subcycle Resolution
16.0 Serial Peripheral Interface (SPI)
- FIGURE 16-1: SPI1 Module Block Diagram (Standard Buffer Mode)
- FIGURE 16-2: SPI1 Module Block Diagram (Enhanced Buffer Mode)
- Register 16-1: SPIxSTAT: SPIx Status and Control Register
- Register 16-2: SPIxCON1: SPIx Control Register 1
- Register 16-3: SPIxCON2: SPIx Control Register 2
- EQUATION 16-1: Relationship Between Device and SPIx Clock Speed(1)
- TABLE 16-1: Sample SCKx Frequencies(1,2)
17.0 Inter-Integrated Circuit (I2C)
- 17.1 Pin Remapping Options
- 17.2 Communicating as a Master in a Single Master Environment
  - FIGURE 17-1: I2C Block Diagram (I2C1 Module is Shown)
- 17.3 Setting Baud Rate When Operating as a Bus Master
  - EQUATION 17-1: Computing Baud Rate Reload Value(1)
- 17.4 Slave Address Masking
18.0 Universal Asynchronous Receiver Transmitter (UART)
- FIGURE 18-1: UARTx Simplified Block Diagram
- 18.1 UARTx Baud Rate Generator (BRG)
- 18.2 Transmitting in 8-Bit Data Mode
- 18.3 Transmitting in 9-Bit Data Mode
- 18.4 Break and Sync Transmit Sequence
- 18.5 Receiving in 8-Bit or 9-Bit Data Mode
- 18.6 Operation of UxCTS and UxRTS Control Pins
- 18.7 Infrared Support
  - 18.7.1 External IrDA Support – IrDA Clock Output
  - 18.7.2 Built-in IrDA Encoder and Decoder
19.0 Real-Time Clock and Calendar (RTCC)
- 19.1 RTCC Source Clock
  - FIGURE 19-1: RTCC Block Diagram
- 19.2 RTCC Module Registers
- 19.3 Calibration
  - EQUATION 19-1:
- 19.4 Alarm
  - 19.4.1 Configuring the Alarm
  - 19.4.2 Alarm Interrupt
    - FIGURE 19-2: Alarm Mask Settings
- 19.5 POWER CONTROL
20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
- FIGURE 20-1: CRC Block Diagram
- FIGURE 20-2: CRC Shift Engine Detail
- 20.1 User Interface
- 20.2 Registers
21.0 High/Low-Voltage Detect (HLVD)
- FIGURE 21-1: High/Low-Voltage Detect (HLVD) Module Block Diagram
- Register 21-1: HLVDCON: High/Low-Voltage Detect Control Register
22.0 12-Bit A/D Converter with Threshold Detect
- FIGURE 22-1: 12-Bit A/D Converter Block Diagram
- 22.1 A/D Control Registers
  - 22.1.1 Control Registers
  - 22.1.2 A/D Result Buffers
- 22.2 A/D Sampling Requirements
  - EQUATION 22-1: A/D Conversion Clock Period
  - FIGURE 22-2: 12-Bit A/D Converter Analog Input Model
- 22.3 Transfer Function
  - FIGURE 22-3: 12-bit A/D Transfer Function
- 22.4 Buffer Data Formats
23.0 Comparator Module
- FIGURE 23-1: Comparator x Module Block Diagram
- FIGURE 23-2: Individual Comparator Configurations
- Register 23-1: CMxCON: Comparator x Control Registers
- Register 23-2: CMSTAT: Comparator x Module Status Register
24.0 Comparator Voltage Reference
- 24.1 Configuring the Comparator Voltage Reference
  - FIGURE 24-1: Comparator Voltage Reference Block Diagram
  - Register 24-1: CVRCON: Comparator Voltage Reference Control Register
25.0 Charge Time Measurement Unit (CTMU)
- 25.1 Measuring Capacitance
  - EQUATION 25-1:
  - FIGURE 25-1: Typical Connections and Internal Configuration for Capacitance Measurement
- 25.2 Measuring Time
  - FIGURE 25-2: Typical Connections and Internal Configuration for Time Measurement
- 25.3 Pulse Generation and Delay
26.0 Special Features
- 26.1 Configuration Bits
- 26.2 On-Chip Voltage Regulator
  - 26.2.1 Voltage Regulator Tracking Mode and Low-Voltage Detection
  - 26.2.2 On-Chip Regulator and POR
    - FIGURE 26-1: Connections for the On-Chip Regulator
- 26.3 Watchdog Timer (WDT)
  - 26.3.1 Windowed Operation
  - 26.3.2 Control Register
    - FIGURE 26-2: WDT Block Diagram
- 26.4 Deep Sleep Watchdog Timer (DSWDT)
- 26.5 Program Verification and Code Protection
- 26.6 In-Circuit Serial Programming
- 26.7 In-Circuit Debugger
27.0 Development Support
- 27.1 MPLAB X Integrated Development Environment Software
- 27.2 MPLAB XC Compilers
- 27.3 MPASM Assembler
- 27.4 MPLINK Object Linker/ MPLIB Object Librarian
- 27.5 MPLAB Assembler, Linker and Librarian for Various Device Families
- 27.6 MPLAB X SIM Software Simulator
- 27.7 MPLAB REAL ICE In-Circuit Emulator System
- 27.8 MPLAB ICD 3 In-Circuit Debugger System
- 27.9 PICkit 3 In-Circuit Debugger/ Programmer
- 27.10 MPLAB PM3 Device Programmer
- 27.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits
- 27.12 Third-Party Development Tools
28.0 Instruction Set Summary
- TABLE 28-1: Symbols Used in Opcode Descriptions
- TABLE 28-2: Instruction Set Overview
29.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 29.1 DC Characteristics
- 29.2 AC Characteristics and Timing Parameters
30.0 DC and AC Characteristics Graphs and Tables
- 30.1 Characteristics for Industrial Temperature Devices (-40°C to +85°C)
- 30.2 Characteristics for Extended Temperature Devices (-40°C to +125°C)
31.0 Packaging Information
- 31.1 Package Marking Information
- 31.2 Package Details
Appendix A: Revision History
- Revision A (March 2011)
- Revision B (April 2011)
- Revision C (April 2012)
- Revision D (March 2013)
- Revision E (October 2017)
INDEX
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 2011-2017 Microchip Technology Inc. DS30009995E-page 213

PIC24FV32KA304 FAMILY

bit 0

ALTS:

Alternate Input Sample Mode Select bit

1 = Uses channel input selects for Sample A on the first sample and Sample B on the next sample

0 = Always uses channel input selects for Sample A

Note 1:

This is only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only

used when BUFM = 1.

The voltage reference setting will not be within the specification with V

below 4.5V.

The voltage reference setting will not be within the specification with V

below 2.3V.