Datasheet

 2011-2017 Microchip Technology Inc. DS30009995E-page 171
PIC24FV32KA304 FAMILY
17.3 Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator (BRG) reload
value, use Equation 17-1.
EQUATION 17-1: COMPUTING BAUD RATE
RELOAD VALUE
(1)
17.4 Slave Address Masking
The I2CxMSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2CxMSK register causes the slave
module to respond, whether the corresponding
address bit value is ‘0’ or ‘1’. For example, when
I2CxMSK is set to ‘00100000’, the slave module will
detect both addresses: ‘0000000’ and ‘00100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2C1CON<11>).
TABLE 17-1: I
2
C CLOCK RATES
(1)
TABLE 17-2: I
2
C RESERVED ADDRESSES
(1)
I2CxBRG
F
CY
F SCL
------------
F
CY
10 000 000
------------------------------–


1–=
F
SCL
F CY
I2CxBRG 1
F CY
10 000 000
------------------------------++
----------------------------------------------------------------------
=
or
Note 1:
Based on F CY = F OSC /2; Doze mode and PLL
are disabled.
Note: As a result of changes in the I
2
C protocol,
the addresses in Tabl e 1 7-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings that include any of these
addresses.
Required
System
F SCL
F CY
I2CxBRG Value
Actual
F
SCL
(Decimal) (Hexadecimal)
100 kHz 16 MHz 157 9D 100 kHz
100 kHz 8 MHz 78 4E 100 kHz
100 kHz 4 MHz 39 27 99 kHz
400 kHz 16 MHz 37 25 404 kHz
400 kHz 8 MHz 18 12 404 kHz
400kHz 4MHz 9 9 385kHz
400kHz 2MHz 4 4 385kHz
1 MHz 16 MHz 13 D 1.026 MHz
1MHz 8MHz 6 6 1.026MHz
1MHz 4MHz 3 3 0.909MHz
Note 1: Based on F
CY = F OSC /2; Doze mode and PLL are disabled.
Slave
Address
R/W
Bit
Description
0000 000 0 General Call Address
(2)
0000 000 1 Start Byte
0000 001 x CBus Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte
(3)
Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.
2: This address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.