Datasheet

 2011-2017 Microchip Technology Inc. DS30009995E-page 155
PIC24FV32KA304 FAMILY
15.3.1 PWM PERIOD
In Edge-Aligned PWM mode, the period is specified by
the value of the OCxRS register. In Center-Aligned
PWM mode, the period of the synchronization source,
such as the Timers’ PRy, specifies the period. The
period in both cases can be calculated using
Equation 15-1.
EQUATION 15-1: CALCULATING THE PWM
PERIOD
(1)
15.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a period is complete.
This provides a double buffer for the PWM duty cycle
and is essential for glitchless PWM operation.
Some important boundary parameters of the PWM duty
cycle include:
• Edge-Aligned PWM:
- If OCxR and OCxRS are loaded with 0000h,
the OCx pin will remain low (0% duty cycle).
- If OCxRS is greater than OCxR, the pin will
remain high (100% duty cycle).
• Center-Aligned PWM (with TMRy as the
Sync source):
- If OCxR, OCxRS and PRy are all loaded with
0000h, the OCx pin will remain low
(0% duty cycle).
- If OCxRS is greater than PRy, the pin will go
high (100% duty cycle).
See Example 15-3 for PWM mode timing details.
Table 15-1 and Table 15-2 show example PWM
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
EQUATION 15-2: CALCULATION FOR MAXIMUM PWM RESOLUTION
(1)
EQUATION 15-3: PWM PERIOD AND DUTY CYCLE CALCULATIONS
(1)
PWM Period = [Value + 1] x T CY x (Prescaler Value)
Where:
Note 1: Based on T CY = T OSC * 2; Doze mode and
PLL are disabled.
(if TMRy is the Sync source).
and can be PRy in Center-Aligned PWM mode
Value = OCxRS in Edge-Aligned PWM mode
(
)
Maximum PWM Resolution (bits) =
F
CY
F PWM • (Prescale Value)
log
10
log
10
(2)
bits
Note 1: Based on F CY = F OSC /2; Doze mode and PLL are disabled.
1. Find the OCxRS register value for a desired PWM frequency of 52.08 kHz, where F OSC = 8 MHz with PLL (32 MHz device
clock rate) and a prescaler setting of 1:1 using Edge-Aligned PWM mode:
T CY = 2 • T OSC = 62.5 ns
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s
PWM Period = (OCxRS + 1) • T
CY • (OCx Prescale Value)
19.2 s = (OCxRS + 1) • 62.5 ns • 1
OCxRS = 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
PWM Resolution = log
10
(F CY /F PWM )/log
10
2) bits
=(log
10
(16 MHz/52.08 kHz)/log
10
2) bits
= 8.3 bits
Note 1: Based on T
CY = 2 * T OSC ; Doze mode and PLL are disabled.