Datasheet

PIC24FV32KA304 FAMILY
DS30009995E-page 126  2011-2017 Microchip Technology Inc.
10.2.2 IDLE MODE
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.6
“Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
10.2.3 INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
10.2.4 DEEP SLEEP MODE
In PIC24FV32KA304 family devices, Deep Sleep mode
is intended to provide the lowest levels of power
consumption available without requiring the use of
external switches to completely remove all power from
the device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR Event
•MCLR
Event
• RTCC Alarm (if the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) Time-out
• Ultra Low-Power Wake-up (ULPWU) Event
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
10.2.4.1 Entering Deep Sleep Mode
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register and then executing a Sleep com-
mand (PWRSAV #SLEEP_MODE). An unlock sequence
is required to set the DSEN bit. Once the DSEN bit has
been set, there is no time limit before the SLEEP com-
mand can be executed. The DSEN bit is automatically
cleared when exiting the Deep Sleep mode.
The sequence to enter Deep Sleep mode is:
1. If the application requires the Deep Sleep WDT,
enable it and configure its clock source. For
more information on Deep Sleep WDT, see
Section 10.2.4.5 “Deep Sleep WDT”.
2. If the application requires Deep Sleep BOR,
enable it by programming the DSLPBOR
Configuration bit (FDS<6>).
3. If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module For more information on RTCC,
see Section 19.0 “Real-Time Clock and
Calendar (RTCC)”.
4. If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
5. Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
6. Enter Deep Sleep mode by issuing a PWRSAV #0
instruction.
Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.
To set the DSEN bit, the unlock sequence in
Example 10-2 is required:
EXAMPLE 10-2: THE UNLOCK SEQUENCE
Note: To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 T
CY
after clearing the RELEASE bit.
Note: An unlock sequence is required to set the
DSEN bit.
//Disable Interrupts For 5 instructions
asm volatile(“disi #5”);
//Issue Unlock Sequence
asm volatile
mov #0x55, W0;
mov W0, NVMKEY;
mov #0xAA, W1;
mov W1, NVMKEY;
bset DSCON, #DSEN