Datasheet

 2011-2017 Microchip Technology Inc. DS30009995E-page 11
PIC24FV32KA304 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FV16KA301, PIC24F16KA301
• PIC24FV16KA302, PIC24F16KA302
• PIC24FV16KA304, PIC24F16KA304
• PIC24FV32KA301, PIC24F32KA301
• PIC24FV32KA302, PIC24F32KA302
• PIC24FV32KA304, PIC24F32KA304
The PIC24FV32KA304 family introduces a new line of
extreme low-power Microchip devices. This is a 16-bit
microcontroller family with a broad peripheral feature
set and enhanced computational performance. This
family also offers a new migration option for those
high-performance applications which may be out-
growing their 8-bit platforms, but do not require the
numerical processing power of a Digital Signal
Processor (DSP).
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC
®
digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element Working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32-bit by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as C
• Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
All of the devices in the PIC24FV32KA304 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
features include:
• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing users to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
• Instruction-Based Power-Saving Modes: There
are three instruction-based power-saving modes:
- Idle Mode: The core is shut down while
leaving the peripherals active.
- Sleep Mode: The core and peripherals that
require the system clock are shut down,
leaving the peripherals that use their own
clock, or the clock from other devices, active.
- Deep Sleep Mode: The core, peripherals
(except RTCC and DSWDT), Flash and
SRAM are shut down.
1.1.3 OSCILLATOR OPTIONS AND
FEATURES
The PIC24FV32KA304 family offers five different
oscillator options, allowing users a range of choices in
developing application hardware. These include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• Two Fast Internal oscillators (FRCs): One with a
nominal 8 MHz output and the other with a
nominal 500 kHz output. These outputs can also
be divided under software control to provide clock
speed as low as 31 kHz or 2 kHz.
• A Phase Locked Loop (PLL) frequency multiplier,
available to the external Oscillator modes and the
8 MHz FRC oscillator, which allows clock speeds
of up to 32 MHz.
• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.