PIC24FV32KA304 FAMILY 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology Power Management Modes Peripheral Features • • • • • Hardware Real-Time Clock and Calendar (RTCC): - Provides clock, calendar and alarm functions - Can run in Deep Sleep mode - Can use 50/60 Hz power line input as clock source • Programmable 32-Bit Cyclic Redundancy Check (CRC) • Multiple Serial Communication modules: - Two 3/4-wire SPI modules - Two I2C modules with multi-master/slave support - Two
PIC24FV32KA304 FAMILY EE Data (bytes) Timers 16-Bit Capture Input Compare/PWM Output UART w/ IrDA® SPI I2C 12-Bit A/D (ch) Comparators CTMU (ch) RTCC • Wide Operating Voltage Range: - 1.8V to 3.6V (PIC24F devices) - 2.0V to 5.
PIC24FV32KA304 FAMILY 20-Pin SPDIP/SSOP/SOIC(1) MCLR/RA5 RA0 RA1 RB0 RB1 RB2 RA2 RA3 RB4 RA4 1 2 3 4 5 6 7 8 9 10 24FVXXKA301 24FXXKA301 Pin Diagrams 20 19 18 17 16 15 14 13 12 11 VDD VSS RB15 RB14 RB13 RB12 RA6 or VCAP RB9 RB8 RB7 Pin Features Pin PIC24FVXXKA301 PIC24FXXKA301 1 MCLR/VPP/RA5 2 PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0 PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0 3 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1 4 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/
PIC24FV32KA304 FAMILY Pin Diagrams MCLR/RA5 RA0 RA1 RB0 RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FVXXKA302 PIC24FXXKA302 28-Pin SPDIP/SSOP/SOIC(2) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD Vss RB15 RB14 RB13 RB12 RB11 RB10 RA6 or VCAP RA7 RB9 RB8 RB7 RB6 Pin Features Pin PIC24FVXXKA302 PIC24FXXKA302 1 MCLR/VPP/RA5 2 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 MCLR/VPP/RA5 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 3 CVREF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1
PIC24FV32KA304 FAMILY Pin Diagrams RA1 RA0 MCLR/RA5 VDD VSS RB15 RB14 28-Pin QFN(1,3) 28 27 26 25 24 23 22 1 2 3 4 5 6 7 21 20 PIC24FVXXKA302 19 PIC24FXXKA302 18 17 16 15 8 9 10 11 12 13 14 RB13 RB12 RB11 RB10 RA6 or VCAP RA7 RB9 RB4 RA4 VDD RB5 RB6 RB7 RB8 RB0 RB1 RB2 RB3 VSS RA2 RA3 Pin Features Pin PIC24FVXXKA302 PIC24FXXKA302 1 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 2 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 PGEC1/AN3/C1IN
PIC24FV32KA304 FAMILY Pin Diagrams Pin Features PIC24FVXXKA304 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 RB6 RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 44-Pin TQFP/QFN Pin (1,3) PIC24FVXXKA304 PIC24FXXKA304 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 Vss VDD RC2 RC1 RC0 RB3 RB2 RA10 RA11 RB14 RB15 VSS VDD MCLR/RA5 RA0 RA1 RB0 RB1 RB9 RC6 RC7 RC8 RC9 RA7 RA6 or VCAP RB10 RB11 RB12 RB13 Legend: Pin numbers in bold indicate pin function differences
PIC24FV32KA304 FAMILY Pin Diagrams Pin Features Pin 48-Pin UQFN(1,3) 1 2 3 4 5 6 7 8 9 10 11 12 PIC24FVXXKA304 PIC24FXXKA304 36 35 34 33 32 31 30 29 28 27 26 25 RB4 RA8 RA3 RA2 N/C VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA11 RB14 RB15 VSS/AVSS VDD/AVDD MCLR/RA5 N/C RA0 RA1 RB0 RB1 13 14 15 16 17 18 19 20 21 22 23 24 RB9 RC6 RC7 RC8 RC9 RA7 RA6 or VCAP N/C RB10 RB11 RB12 RB13 48 47 46 45 44 43 42 41 40 39 38 37 RB8 RB7 RB6 RB5 N/C VDD VSS RC5 RC4 RC3 RA9 RA4 PIC24FVXXKA304 PIC24FXXKA304 1 SDA1/T1CK/U
PIC24FV32KA304 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 23 3.0 CPU ....................................................................................................
PIC24FV32KA304 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 10 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • • • PIC24FV16KA301, PIC24F16KA301 PIC24FV16KA302, PIC24F16KA302 PIC24FV16KA304, PIC24F16KA304 PIC24FV32KA301, PIC24F32KA301 PIC24FV32KA302, PIC24F32KA302 PIC24FV32KA304, PIC24F32KA304 The PIC24FV32KA304 family introduces a new line of extreme low-power Microchip devices.
PIC24FV32KA304 FAMILY The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.
PIC24FV32KA304 FAMILY PIC24FV32KA302 PIC24FV16KA304 PIC24FV32KA304 Program Memory (bytes) 16K 32K 16K 32K 16K 32K Program Memory (instructions) 5632 11264 5632 11264 5632 11264 Features Operating Frequency PIC24FV16KA302 PIC24FV32KA301 DEVICE FEATURES FOR THE PIC24FV32KA304 FAMILY PIC24FV16KA301 TABLE 1-1: DC – 32 MHz Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/ NMI traps) 30 (26/4) I/O Ports Total I/O Pins PORTA<5:0> PORTB<15:12,9:
PIC24FV32KA304 FAMILY Operating Frequency PIC24F32KA304 PIC16F16KA304 PIC24F32KA302 PIC24F16KA302 Features PIC24F32KA301 DEVICE FEATURES FOR THE PIC24F32KA304 FAMILY PIC24F16KA301 TABLE 1-2: DC – 32 MHz Program Memory (bytes) 16K 32K 16K 32K 16K 32K Program Memory (instructions) 5632 11264 5632 11264 5632 11264 Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/ NMI traps) 30 (26/4) I/O Ports Total I/O Pins PORTA<6:0>, PORTB<15:12, 9:7, 4
PIC24FV32KA304 FAMILY FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller 16 16 8 16 Data Latch PSV and Table Data Access Control Block Data RAM PCL PCH Program Counter Stack Repeat Control Control Logic Logic 23 Address Latch PORTA(1) RA<0:7> 16 23 16 Read AGU Write AGU Address Latch Program Memory PORTB(1) RB<0:15> Data EEPROM Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTC(1) RC<9:0> Inst Register Instruction Decode and Con
Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS F FV Pin Number Pin Number I/O Buffer 21 I ANA 22 I ANA 21 23 I ANA 22 24 I ANA 3 23 25 I ANA 7 4 24 26 I ANA — — — 25 27 I ANA 28 — — — 26 28 I ANA 27 29 — — — 27 29 I ANA 23 15 16 18 26 23 15 16 I ANA 25 22 14 15 17 25 22 14 15 I ANA 24 21 11 12 16 24 21 11 12 I ANA 23 20 10 11 15 23 20 10 11 I ANA 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN
2011-2017 Microchip Technology Inc.
Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number I/O Buffer 47 I ST 46 I ST 37 40 I ST 38 41 I ST 41 45 I ST 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN CN23 11 16 13 43 47 11 16 13 43 CN24 –- 15 12 42 46 –- 15 12 42 CN25 –- — — 37 40 –- –- –- CN26 –- — — 38 41 –- –-
2011-2017 Microchip Technology Inc.
Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number I/O Buffer 21 I/O ST 22 I/O ST ST 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN RA0 2 2 27 19 21 2 2 27 19 RA1 3 3 28 20 22 3 3 28 20 RA2 7 9 6 30 33 7 9 6 30 33 I/O RA3 8 10 7 31 34 8 10 7 31 34 I/O ST RA4 10 12 9 34
2011-2017 Microchip Technology Inc.
Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number I/O Buffer Description 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN T1CK 13 18 15 1 1 13 18 15 1 1 I ST Timer1 Clock T2CK 18 26 23 15 16 18 26 23 15 16 I ST Timer2 Clock T3CK 18 26 23 15 16 18 26 23 15 16 I ST Timer3 Clock T4CK 6 6 3 23 25 6 6 3 23 25 I ST Timer4 Clock T5CK 6 6 3 23 25 6 6 3 23 25 I ST Timer5 Clock U1CTS 12
PIC24FV32KA304 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VCAP pins (see Section 2.
PIC24FV32KA304 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24FV32KA304 FAMILY Voltage Regulator Pin (VCAP) Note: This section applies only to PIC24F K devices with an On-Chip Voltage Regulator. Refer to Section 29.0 “Electrical Characteristics” for information on VDD and VDDCORE. FIGURE 2-3: Some of the PIC24F K devices have an internal Voltage Regulator. These devices have the Voltage Regulator output brought out on the VCAP pin.
PIC24FV32KA304 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal Voltage Regulator of this microcontroller.
PIC24FV32KA304 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 28 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the “dsPIC33/PIC24 Family Reference Manual”, “CPU” (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24FV32KA304 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCL PCH Program Counter Loop Stack Control Control Logic Logic 23 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory Data EEPROM EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Literal Data 16 Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 1
PIC24FV32KA304 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL 2 1 0 RA N OV Z C 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Regi
PIC24FV32KA304 FAMILY 3.
PIC24FV32KA304 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — R/C-0, HSC (1) IPL3 R/W-0 U-0 U-0 PSV — — bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority
PIC24FV32KA304 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24FV32KA304 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and busing. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh).
PIC24FV32KA304 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In the PIC24FV32KA304 family, the data EEPROM is mapped to the top of the user program memory space, starting at address, 7FFE00, and expanding up to address, 7FFFFF. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented.
PIC24FV32KA304 FAMILY 4.2 PIC24FV32KA304 family devices implement a total of 1024 words of data memory. If an EA points to a location outside of this area, an all zero word or byte will be returned. Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 4-3. 4.2.
PIC24FV32KA304 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address (EA) calculations are internally scaled to step through word-aligned memory.
CPU CORE REGISTERS MAP File Name Start Addr WREG0 0000 WREG0 0000 WREG1 0002 WREG1 0000 WREG2 0004 WREG2 0000 WREG3 0006 WREG3 0000 WREG4 0008 WREG4 0000 WREG5 000A WREG5 0000 WREG6 000C WREG6 0000 WREG7 000E WREG7 0000 WREG8 0010 WREG8 0000 WREG9 0012 WREG9 0000 WREG10 0014 WREG10 0000 WREG11 0016 WREG11 0000 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG12 0018 WREG1
2011-2017 Microchip Technology Inc.
File Name Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 INTCON1 0080 NSTDIS Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 All Resets 2011-2017 Microchip Technology Inc.
2011-2017 Microchip Technology Inc.
File Name Addr OC1CON1 0190 OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 — — OCSIDL OC1CON2 0192 FLTMD FLTOUT FLTTRIEN Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 OCINV — DCB1 DCB0 OC32 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC1RS 0194 OC1RS 0000 OC1R 0196 OC1R 0000 OC1TMR 0198 OC
2011-2017 Microchip Technology Inc.
File Name SPIx REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 SPI1STAT 0240 SPIEN — SPISIDL — — SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — SPI1BUF 0248 SPI2STAT 0260 SPIBEC2 SPIBEC1 SPIBEC0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRMPT SPIROV SR1MPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 — — — — — — SPIFE S
2011-2017 Microchip Technology Inc. TABLE 4-14: PORTC REGISTER MAP(1) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 TRISC Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 02D0 — — — — — — TRISC<9:0> 03FF PORTC 02D2 — — — — — — RC<9:0> xxxx LATC 02D4 — — — — — — LATC<9:0> xxxx ODCC 02D6 — — — — — — ODC<9:0> 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
A/D REGISTER MAP File Name Addr ADC1BUF0 0300 ADC1BUF0 xxxx ADC1BUF1 0302 ADC1BUF1 xxxx ADC1BUF2 0304 ADC1BUF2 xxxx ADC1BUF3 0306 ADC1BUF3 xxxx ADC1BUF4 0308 ADC1BUF4 xxxx ADC1BUF5 030A ADC1BUF5 xxxx ADC1BUF6 030C ADC1BUF6 xxxx ADC1BUF7 030E ADC1BUF7 xxxx ADC1BUF8 0310 ADC1BUF8 xxxx ADC1BUF9 0312 ADC1BUF9 xxxx ADC1BUF10 0314 ADC1BUF10 xxxx ADC1BUF11 0316 ADC1BUF11 xxxx ADC1BUF12 0318 ADC1BUF12 xxxx ADC1BUF13 031A ADC1BUF13 xxxx ADC1BUF14 031C ADC1BUF14
2011-2017 Microchip Technology Inc.
File Name CRC REGISTER MAP Bit 15 Bit 14 Bit 13 CRCCON1 0640 CRCEN — CSIDL CRCCON2 0642 — — — CRCXORL 0644 CRCXORH 0646 X<31:16> CRCDATL 0648 CRCDATL xxxx CRCDATH 064A CRCDATH xxxx CRCWDATL 064C CRCWDATL xxxx CRCWDATH 064E CRCWDATH xxxx Legend: Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 Bit 1 Bit 0 — — — 0
2011-2017 Microchip Technology Inc. TABLE 4-24: File Name NVM REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 NVMCON 0760 WR WREN WRERR PGMONLY — — — — — ERASE NVMOP5 NVMKEY 0766 — — — — — — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 NVMKEY All Resets(1) 0000 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Reset value shown is for POR only.
PIC24FV32KA304 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a Working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24FV32KA304 FAMILY TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0>(2) Data EA<14:
PIC24FV32KA304 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. It also offers a direct method of reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.
PIC24FV32KA304 FAMILY In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space.
PIC24FV32KA304 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into a 16K word page (in PIC24FV16KA3XX devices) and a 32K word page (in PIC24FV32KA3XX devices) of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 56 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Flash programming, refer to the “dsPIC33/PIC24 Family Reference Manual”, “PIC24F Flash Program Memory” (DS30009715). The PIC24FV32KA304 family of devices contains internal Flash program memory for storing and executing application code.
PIC24FV32KA304 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time, and to program one row at a time. It is also possible to program single words. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks, and single row write block (96 bytes) are edge-aligned from the beginning of program memory.
PIC24FV32KA304 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY(4) — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: SO = Settable Only bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, r
PIC24FV32KA304 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is as follows: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOPx bits (NVMCON<5:0>) to ‘011000’ to configure for row erase.
PIC24FV32KA304 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE // C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = 0x1234; // Global variable located in Pgm Memory unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); offset = __builtin_tbloffset(&progAddr); // Initialize PM Page Boundary SFR // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase b
PIC24FV32KA304 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr = 0x1234; // Global variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write //Set up NVMCON for row programming NVMCON = 0x4001; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = __builti
PIC24FV32KA304 FAMILY 6.0 Note: DATA EEPROM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Data EEPROM, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Data EEPROM” (DS39720). The data EEPROM memory is a Nonvolatile Memory (NVM), separate from the program and volatile data RAM.
PIC24FV32KA304 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 bit 7 bit 0 Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is u
PIC24FV32KA304 FAMILY 6.3 NVM Address Register 6.4 As with Flash program memory, the NVM Address registers, NVMADRU and NVMADR, form the 24-bit Effective Address (EA) of the selected row or word for data EEPROM operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA. These registers are not mapped into the Special Function Register (SFR) space.
PIC24FV32KA304 FAMILY 6.4.1 ERASE DATA EEPROM The data EEPROM can be fully erased, or can be partially erased, at three different sizes: one word, four words or eight words. The bits, NVMOP<1:0> (NVMCON<1:0>), decide the number of words to be erased. To erase partially from the data EEPROM, the following sequence must be followed: 1. 2. 3. 4. 5. 6. Configure NVMCON to erase the required number of words: one, four or eight. Load TBLPAG and WREG with the EEPROM address to be erased.
PIC24FV32KA304 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the address registers do not need to be configured because this operation affects the entire data EEPROM. The following sequence helps in performing a bulk erase: To write a single word in the data EEPROM, the following sequence must be followed: 1. 2. 2. 3. 4. 5. Configure NVMCON to Bulk Erase mode. Clear the NVMIF status bit and enable the NVM interrupt (optional).
PIC24FV32KA304 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the Table Read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location, followed by a TBLRDL instruction.
PIC24FV32KA304 FAMILY 7.0 RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Resets, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Reset with Programmable Brown-out Reset” (DS39728). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24FV32KA304 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 7-1: R/W-0, HS R/W-0, HS R/W-0 R/W-0 U-0 R/C-0, HS R/W-0 R/W-0 TRAPR IOPUWR SBOREN RETEN(3) — DPSLP CM PMSLP bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bi
PIC24FV32KA304 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 7-1: bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode b
PIC24FV32KA304 FAMILY 7.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the Oscillator Configuration bits. For more information, see Section 9.0 “Oscillator Configuration”. TABLE 7-2: OSCILLATOR SELECTION vs.
PIC24FV32KA304 FAMILY 7.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24FV32KA304 FAMILY 7.5.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘0’ in the software immediately after any POR event.
PIC24FV32KA304 FAMILY 8.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Interrupts” (DS70000600). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU.
PIC24FV32KA304 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Ve
PIC24FV32KA304 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error Reserved 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source Vector Number IVT Address Interrupt Bit Locations AIVT Address Flag E
PIC24FV32KA304 FAMILY 8.3 Interrupt Control and Status Registers The PIC24FV32KA304 family of devices implements a total of 23 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0, IFS1, IFS3 and IFS4 IEC0, IEC1, IEC3 and IEC4 IPC0 through IPC5, IPC7 and IPC15 through IPC19 • INTTREG Global Interrupt Enable (GIE) control functions are controlled from INTCON1 and INTCON2.
PIC24FV32KA304 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9
PIC24FV32KA304 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Prior
PIC24FV32KA304 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interru
PIC24FV32KA304 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = U
PIC24FV32KA304 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS NVMIF bit 15 U-0 — R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF R/W-0, HS SPI1IF R/W-0, HS SPF1IF R/W-0, HS T3IF bit 8 R/W-0, HS T2IF bit 7 R/W-0, HS OC2IF R/W-0, HS IC2IF U-0 — R/W-0, HS T1IF R/W-0, HS OC1IF R/W-0, HS IC1IF R/W-0, HS INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 HS = Hardware Sett
PIC24FV32KA304 FAMILY REGISTER 8-5: bit 2 bit 1 bit 0 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS30009995E-page 84
PIC24FV32KA304 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS U2TXIF bit 15 R/W-0, HS U2RXIF U-0 — U-0 — R/W-0, HS INT2IF R/W-0, HS T5IF R/W-0, HS T4IF Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0, HS OC3IF U-0 — bit 8 U-0 — R/W-0, HS INT1IF R/W-0, HS CNIF bit 7 bit 15 U-0 — R/W-0, HS CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 HS = Hardware Settable bit W = Writable bit U = Un
PIC24FV32KA304 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0, HS U-0 U-0 U-0 R/W-0, HS R/W-0, HS — — IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IF: Input Capture Channel 3 In
PIC24FV32KA304 FAMILY REGISTER 8-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS U-0 — — — — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calen
PIC24FV32KA304 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: C
PIC24FV32KA304 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — ULPWUIF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Stat
PIC24FV32KA304 FAMILY REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 NVMIE bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read
PIC24FV32KA304 FAMILY REGISTER 8-11: bit 1 bit 0 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY REGISTER 8-12: R/W-0 U2TXIE bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2RXIE R/W-0 INT2IE R/W-0 T5IE R/W-0 T4IE U-0 — U-0 — R/W-0 INT1IE R/W-0 CNIE bit 7 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 OC3IE U-0 — bit 8 U-0 — bit 15 U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is c
PIC24FV32KA304 FAMILY REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — — IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt requ
PIC24FV32KA304 FAMILY REGISTER 8-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrup
PIC24FV32KA304 FAMILY REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt reques
PIC24FV32KA304 FAMILY REGISTER 8-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ULPWUIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Bit 1 = Interrupt request is ena
PIC24FV32KA304 FAMILY REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1
PIC24FV32KA304 FAMILY REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrup
PIC24FV32KA304 FAMILY REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FV32KA304 FAMILY REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Inte
PIC24FV32KA304 FAMILY REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CN
PIC24FV32KA304 FAMILY REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrup
PIC24FV32KA304 FAMILY REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T4IP2 T4IP1 T4IP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 =
PIC24FV32KA304 FAMILY REGISTER 8-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FV32KA304 FAMILY REGISTER 8-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Prio
PIC24FV32KA304 FAMILY REGISTER 8-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Event Interrupt Priority bits
PIC24FV32KA304 FAMILY REGISTER 8-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP <2:0>: Master I2C2 E
PIC24FV32KA304 FAMILY REGISTER 8-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority b
PIC24FV32KA304 FAMILY REGISTER 8-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC
PIC24FV32KA304 FAMILY REGISTER 8-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
PIC24FV32KA304 FAMILY REGISTER 8-32: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — ULPWUIP2 ULPWUIP1 ULPWUIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 6-4 ULPWUIP<2:0>: Ultra Low-Power Wake-up Interrupt Priority
PIC24FV32KA304 FAMILY REGISTER 8-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interr
PIC24FV32KA304 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 114 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 9.0 • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode. When using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown.
PIC24FV32KA304 FAMILY 9.1 CPU Clocking Scheme 9.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24FV32KA304 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit.
PIC24FV32KA304 FAMILY 9.3 The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): The FRC Oscillator Tune register (Register 9-3) allows the user to fine tune the FRC oscillator over a range of approximately ±5.25%.
PIC24FV32KA304 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24FV32KA304 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit, a
PIC24FV32KA304 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0>(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 x
PIC24FV32KA304 FAMILY 9.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 9.4.1 The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits.
PIC24FV32KA304 FAMILY The following code sequence for a clock switch is recommended: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8>, in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24FV32KA304 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Referenc
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 124 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 10.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “dsPIC33/PIC24 Family Reference Manual”, ”Power-Saving Features with Deep Sleep” (DS39727). The PIC24FV32KA304 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24FV32KA304 FAMILY 10.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.6 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24FV32KA304 FAMILY 10.2.4.2 Exiting Deep Sleep Mode Deep Sleep mode exits on any one of the following events: • A POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. • A DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. • An RTCC alarm (if RTCEN = 1). • An assertion (‘0’) of the MCLR pin.
PIC24FV32KA304 FAMILY 10.2.4.5 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (FDS<4>). The postscaler options are programmed by the DSWDTPS<3:0> Configuration bits (FDS<3:0>). The minimum time-out period that can be achieved is 2.
PIC24FV32KA304 FAMILY DSCON: DEEP SLEEP CONTROL REGISTER(1) REGISTER 10-1: R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 DSEN — — — — — — RTCCWDIS bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — R/W-0 ULPWUDIS R/W-0 (2) DSBOR R/C-0, HS RELEASE bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 x = Bit is unknown DSEN: Deep Sleep Enable
PIC24FV32KA304 FAMILY DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) REGISTER 10-2: U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR(2,3) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimp
PIC24FV32KA304 FAMILY 10.3 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RB0, allows a slow falling voltage to generate an interrupt without excess current consumption. To use this feature: 1. 2. 3. 4. 5. Charge the capacitor on RB0 by configuring the RB0 pin to an output and setting it to ‘1’. Stop charging the capacitor by configuring RB0 as an input. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the ULPWCON register. Configure Sleep mode. Enter Sleep mode.
PIC24FV32KA304 FAMILY REGISTER 10-3: ULPWCON: ULPWU CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 ULPEN — ULPSIDL — — — — ULPSINK bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 x = Bit is unknown ULPEN: ULPWU Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemen
PIC24FV32KA304 FAMILY 10.4 10.4.3 Voltage Regulator-Based Power-Saving Features The PIC24FV32KA304 series devices have a Voltage Regulator that has the ability to alter functionality to provide power savings. The on-board regulator is made up of two basic modules: the Voltage Regulator (VREG) and the Retention Regulator (RETREG). With the combination of VREG and RETREG, the following power modes are available: 10.4.
PIC24FV32KA304 FAMILY 10.5 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else.
PIC24FV32KA304 FAMILY 11.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O Ports, refer to the “dsPIC33/PIC24 Family Reference Manual”, “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24FV32KA304 family devices do not support Peripheral Pin Select features.
PIC24FV32KA304 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 11.
PIC24FV32KA304 FAMILY REGISTER 11-2: R/W-1 ANSB: ANALOG SELECTION (PORTB) R/W-1 R/W-1 R/W-1 ANSB<15:12> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 — — U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) — ANSB<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 ANSB<15:12>: Analog Select Control bits 1 = Digital input buffer is not active (use for analog input) 0 = Digital in
PIC24FV32KA304 FAMILY 11.2.2 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 11.3 Input Change Notification (ICN) The Input Change Notification function of the I/O ports allows the PIC24FV32KA304 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins.
PIC24FV32KA304 FAMILY 12.0 Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. TIMER1 Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3.
PIC24FV32KA304 FAMILY REGISTER 12-1: R/W-0 T1CON: TIMER1 CONTROL REGISTER U-0 — TON R/W-0 TSIDL U-0 — U-0 U-0 — — R/W-0 T1ECS1 R/W-0 (1) T1ECS0(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Ti
PIC24FV32KA304 FAMILY 13.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Timers” (DS39704). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent,16-bit timers with selectable operating modes.
PIC24FV32KA304 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) Prescaler 1, 8, 64, 256 Gate Sync TCY TGATE TGATE TCS Q 1 Set T3IF (T5IF) Q 0 PR3 (PR5) A/D Event Trigger(2) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4) (1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation.
PIC24FV32KA304 FAMILY FIGURE 13-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) Gate Sync Prescaler 1, 8, 64, 256 TGATE TCS TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TGATE Sync TMR2 (TMR4) Comparator PR2 (PR4) FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) TON Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TGATE TCY Set T3IF (T5IF) 1 0 Reset A/D Event Trigger Equal Q D Q CK TCS TGATE TMR3 (TMR5) Comparator PR
PIC24FV32KA304 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0
PIC24FV32KA304 FAMILY REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 146 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 14.0 INPUT CAPTURE WITH DEDICATED TIMERS Note: 14.1 14.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Input Capture with Dedicated Timer” (DS70000352). All devices in the PIC24FV32KA304 family feature three independent input capture modules.
PIC24FV32KA304 FAMILY 14.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even numbered module (ICy) provides the Most Significant 16 bits.
PIC24FV32KA304 FAMILY REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC24FV32KA304 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unim
PIC24FV32KA304 FAMILY 15.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Output Compare with Dedicated Timer” (DS70005159). All devices in the PIC24FV32KA304 family feature 3 independent output compare modules.
PIC24FV32KA304 FAMILY FIGURE 15-1: OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE) DCBx OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLTx OCFLTx OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxCON2 OCxR OCx Pin Match Event OC Clock Sources Clock Select Increment Comparator OC Output and Fault Logic OCxTMR Reset Match Event Trigger and Sync Sources Trigger and Sync Logic Comparator Match Event OCFA/ OCFB/ CxOUT OCxRS Reset OCx Interrupt DS30009995E-page 152 2011-2017 Microchip Technology
PIC24FV32KA304 FAMILY 15.2 Compare Operations In Compare mode (Figure 15-1), the output compare module can be configured for single-shot or continuous pulse generation. It can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. 3. 4. 5. 6. Calculate the required values for the OCxR and (for Double Compare modes) OCxRS Duty Cycle registers: a) Determine the instruction clock cycle time.
PIC24FV32KA304 FAMILY 15.3 4. Pulse-Width Modulation (PWM) Mode 5. In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare edge-aligned PWM operation: 1. 2. 3. module 6. 7. for Select a clock source by writing the OCTSEL2<2:0> (OCxCON<12:10>) bits.
PIC24FV32KA304 FAMILY 15.3.1 PWM PERIOD 15.3.2 PWM DUTY CYCLE In Edge-Aligned PWM mode, the period is specified by the value of the OCxRS register. In Center-Aligned PWM mode, the period of the synchronization source, such as the Timers’ PRy, specifies the period. The period in both cases can be calculated using Equation 15-1. The PWM duty cycle is specified by writing to the OCxRS and OCxR registers.
PIC24FV32KA304 FAMILY 15.4 The DCBx bits are intended for use with a clock source identical to the system clock. When an OCx module with enabled prescaler is used, the falling edge delay caused by the DCBx bits will be referenced to the system clock period, rather than the OCx module’s period. Subcycle Resolution The DCBx bits (OCxCON2<10:9>) provide for resolution better than one instruction cycle. When used, they delay the falling edge generated from a match event by a portion of an instruction cycle.
PIC24FV32KA304 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 bit 15 bit 8 R/W-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2(1) OCM1(1) OCM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit i
PIC24FV32KA304 FAMILY REGISTER 15-1: bit 2-0 Note 1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx 110 = Edge-Aligned PWM mode on OCx 101 = Double Compare Continuous Pulse mode: Initialize OCx pin low; toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initialize OCx pin low; toggle OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare
PIC24FV32KA304 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1(3) DCB0(3) OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’
PIC24FV32KA304 FAMILY REGISTER 15-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This output compare module(1) 11110 = Reserved 11101 = Reserved 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 100xx = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 011
PIC24FV32KA304 FAMILY 16.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Serial Peripheral Interface, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Serial Peripheral Interface (SPI)” (DS70005185).
PIC24FV32KA304 FAMILY FIGURE 16-1: SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 1:1 to 1:8 Secondary Prescaler SS1/FSYNC1 Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPI1CON1<1:0> SPI1CON1<4:2> Shift Control SDO1 Enable Master Clock bit 0 SDI1 FCY SPI1SR Transfer Transfer SPI1BUF Read SPI1BUF Write SPI1BUF 16 Internal Data Bus DS30009995E-page 162 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY To set up the SPI1 module for the Enhanced Buffer Master (EBM) mode of operation: To set up the SPI1 module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPI1IF bit in the IFS0 register. b) Set the SPI1IE bit in the IEC0 register. c) Write the respective SPI1IPx bits in the IPC2 register. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 1.
PIC24FV32KA304 FAMILY REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 R-0, HSC SRMPT bit 8 R/C-0, HS R/W-0, HSC SPIROV SRXMPT R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read
PIC24FV32KA304 FAMILY REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit has started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
PIC24FV32KA304 FAMILY REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 — bit 15 U-0 — U-0 — R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 SSEN bit 7 R/W-0 CKP R/W-0 MSTEN R/W-0 SPRE2 R/W-0 SPRE1 R/W-0 SPRE0 R/W-0 PPRE1 R/W-0 PPRE0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x =
PIC24FV32KA304 FAMILY REGISTER 16-2: bit 1-0 Note 1: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).
PIC24FV32KA304 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED(1) FCY FSCK = Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PIC24FV32KA304 FAMILY 17.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Inter-Integrated Circuit, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Inter-Integrated Circuit (I2C)” (DS70000195). 17.2 The details of sending a message in Master mode depends on the communication protocols for the device being communicated with.
PIC24FV32KA304 FAMILY FIGURE 17-1: I2C BLOCK DIAGRAM (I2C1 MODULE IS SHOWN) Internal Data Bus I2C1RCV SCL1 Read Shift Clock I2C1RSR LSB SDA1 Address Match Match Detect Write I2C1MSK Write Read I2C1ADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2C1STAT Collision Detect Read Write I2C1CON Acknowledge Generation Read Clock Stretching Write I2C1TRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2C1BRG Read TCY/2 DS30009995E-page 170
PIC24FV32KA304 FAMILY 17.3 Setting Baud Rate When Operating as a Bus Master 17.4 The I2CxMSK register (Register 17-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond, whether the corresponding address bit value is ‘0’ or ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both addresses: ‘0000000’ and ‘00100000’.
PIC24FV32KA304 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
PIC24FV32KA304 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
PIC24FV32KA304 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS IWCOL I2COV R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC D/A P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value
PIC24FV32KA304 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or cleared when a Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected.
PIC24FV32KA304 FAMILY REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits 1 = E
PIC24FV32KA304 FAMILY 18.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Universal Asynchronous Receiver Transmitter, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582).
PIC24FV32KA304 FAMILY 18.1 UARTx Baud Rate Generator (BRG) The UARTx module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. Equation 18-1 provides the formula for computation of the baud rate with BRGH = 0.
PIC24FV32KA304 FAMILY 18.2 1. 2. 3. 4. 5. 6. Set up the UARTx: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UARTx. Set the UTXEN bit (causes a transmit interrupt, two cycles after being set). Write the data byte to the lower byte of the UxTXREG word.
PIC24FV32KA304 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2) UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FV32KA304 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1
PIC24FV32KA304 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HS = Hardware Settable bit C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented b
PIC24FV32KA304 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the t
PIC24FV32KA304 FAMILY REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER U-x — bit 15 U-x — U-x — U-x — W-x W-x W-x W-x U-x — U-x — U-x — W-x W-x W-x W-x UTX8 bit 8 W-x UTX<7:0> bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 bit 7-0 W = Writable bit ‘1’ = Bit is set Unimplemented: Read as ‘0’ UTX8: UARTx Data of the Transmitted Character bit (in 9-bit mode) UTX<7:0>: UARTx Data of the Transmitted Character bits REGISTER 18-4: U-0 — bit 15 R-0, HSC U = Unimplemented
PIC24FV32KA304 FAMILY 19.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Real-Time Clock and Calendar, refer to the “dsPIC33/PIC24 Family Reference Manual”, “RTCC with External Power Control” (DS39745). The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated.
PIC24FV32KA304 FAMILY 19.2 TABLE 19-2: RTCC Module Registers The RTCC module registers are organized into three categories: ALRMPTR <1:0> • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.2.1 To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value Register Window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 19-1).
PIC24FV32KA304 FAMILY 19.2.
PIC24FV32KA304 FAMILY REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute • • • 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses e
PIC24FV32KA304 FAMILY REGISTER 19-2: RTCPWC: RTCC CONFIGURATION REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWCEN PWCPOL PWCCPRE PWCSPRE RTCCLK1(2) RTCCLK0(2) RTCOUT1 RTCOUT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWCEN: Power Control Enable bit 1 = Power
PIC24FV32KA304 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 ALRMEN bit 15 R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ARPT7 bit 7 R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9-8 bit 7-0 W = Writable bit ‘1’ = Bit is set R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is u
PIC24FV32KA304 FAMILY 19.2.
PIC24FV32KA304 FAMILY WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) REGISTER 19-6: U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<
PIC24FV32KA304 FAMILY 19.2.
PIC24FV32KA304 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
PIC24FV32KA304 FAMILY REGISTER 19-11: RTCCSWT: RTCC CONTROL/SAMPLE WINDOW TIMER REGISTER(1) R/W-x PWCSTAB7 bit 15 R/W-x PWCSTAB6 R/W-x PWCSTAB5 R/W-x PWCSTAB4 R/W-x PWCSTAB3 R/W-x PWCSTAB2 R/W-x PWCSTAB1 R/W-x PWCSTAB0 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSAMP7 PWCSAMP6 PWCSAMP5 PWCSAMP4 PWCSAMP3 PWCSAMP2 PWCSAMP1 PWCSAMP0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is u
PIC24FV32KA304 FAMILY 19.3 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value, loaded into the lower half of RCFGCAL, is multiplied by four and will be either added or subtracted from the RTCC timer, once every minute.
PIC24FV32KA304 FAMILY FIGURE 19-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s m s s m m s s 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week d 1000 - Every month 1001 - Every year(1) Note 1: 19.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 198 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 20.0 The programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications.
PIC24FV32KA304 FAMILY 20.1 User Interface 20.1.1 POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN<4:0> bits (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation.
PIC24FV32KA304 FAMILY 20.1.3 DATA SHIFT DIRECTION The LENDIAN bit (CRCCON1<3>) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction of the data that is shifted into the engine.
PIC24FV32KA304 FAMILY REGISTER 20-1: CRCCON1: CRC CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HSC R-1, HSC R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl
PIC24FV32KA304 FAMILY REGISTER 20-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH
PIC24FV32KA304 FAMILY REGISTER 20-3: R/W-0 CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — X<7:1> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’ REGISTER 20-4: R/W-0 x = Bit is unknow
PIC24FV32KA304 FAMILY 21.0 An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. HIGH/LOW-VOLTAGE DETECT (HLVD) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV32KA304 FAMILY REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power En
PIC24FV32KA304 FAMILY 22.0 Note: 12-BIT A/D CONVERTER WITH THRESHOLD DETECT This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 12-Bit A/D Converter with Threshold Detect, refer to the “dsPIC33/PIC24 Family Reference Manual”, “12-Bit A/D Converter with Threshold Detect” (DS39739).
PIC24FV32KA304 FAMILY FIGURE 22-1: 12-BIT A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VREF- VR Select AVDD VR+ 16 VR- VBG Comparator VINH VINL AN0 VRS/H VR+ DAC AN1 12-Bit SAR AN2 Conversion Logic AN3 Data Formatting AN4 VINH AN6 AN7 MUX A AN5 ADC1BUF0: ADC1BUF17 AN8 AD1CON1 AD1CON2 VINL AN9 AD1CON3 AD1CON5 AD1CHS AD1CHITL AN15 CTMU Temp. Sensor CTMU MUX B AN14 AD1CHITH AD1CSSL AD1CSSH VINH VINL Sample Control VBG 0.
PIC24FV32KA304 FAMILY To perform an A/D conversion: 1. 2. Configure the A/D module: a) Configure the port pins as analog inputs and/or select band gap reference inputs (ANS<12:10>, ANS<5:0>). b) Select voltage reference source to match the expected range on the analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:4> and AD1CON3<12:8>).
PIC24FV32KA304 FAMILY 22.1 A/D Control Registers The 12-bit A/D Converter module uses up to 43 registers for its operation. All registers are mapped in the data memory space. 22.1.
PIC24FV32KA304 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL — — MODE12 FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
PIC24FV32KA304 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 — BUFREGEN CSCNA — — bit 15 bit 8 R/W-0 R/W-0 (1) SMPI4 BUFS R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 R/W-0 (1) BUFM bit 7 ALTS bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG<1:0
PIC24FV32KA304 FAMILY REGISTER 22-2: bit 0 AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED) ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on the first sample and Sample B on the next sample 0 = Always uses channel input selects for Sample A Note 1: 2: 3: This is only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only used when BUFM = 1. The voltage reference setting will not be within the specification with VDD below 4.5V.
PIC24FV32KA304 FAMILY REGISTER 22-3: R/W-0 ADRC AD1CON3: A/D CONTROL REGISTER 3 R-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EXTSAM — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source
PIC24FV32KA304 FAMILY REGISTER 22-4: AD1CON5: A/D CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 R/W-0 ASEN(1) LPEN CTMREQ BGREQ — — ASINT1 ASINT0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ASEN: Auto-Scan Enable bit(1) 1 = Auto-scan is enabled 0 = Aut
PIC24FV32KA304 FAMILY REGISTER 22-5: AD1CHS: A/D SAMPLE SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13
PIC24FV32KA304 FAMILY REGISTER 22-6: AD1CHITH: A/D SCAN COMPARE HIT REGISTER (HIGH WORD)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CHH<17:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’.
PIC24FV32KA304 FAMILY AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH WORD)(1) REGISTER 22-8: U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 U-0 U-0 — — CSS<30:26> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CSS<17:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-10 CSS<30:26>: A/D Input Scan Selection bits 1 = Includes corr
PIC24FV32KA304 FAMILY REGISTER 22-10: AD1CTMUENH: A/D CTMU ENABLE REGISTER (HIGH WORD)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CTMEN<17:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’.
PIC24FV32KA304 FAMILY 22.2 A/D Sampling Requirements The analog input model of the 12-bit A/D Converter is shown in Figure 22-2. The total sampling time for the A/D is a function of the holding capacitor charge time. For the A/D Converter to meet its specified accuracy, the Charge Holding Capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin.
PIC24FV32KA304 FAMILY 22.3 • The first code transition occurs when the input voltage is ((VR+) – (VR-))/4096 or 1.0 LSb. • The ‘0000 0000 0001’ code is centered at VR- + (1.5 * ((VR+) – (VR-))/4096). • The ‘0010 0000 0000’ code is centered at VREFL + (2048.5 * ((VR+) – (VR-))/4096). • An input voltage less than VR- + (((VR-) – (VR-))/4096) converts as ‘0000 0000 0000’. • An input voltage greater than (VR-) + (4095 ((VR+) – (VR-))/4096) converts as ‘1111 1111 1111’.
PIC24FV32KA304 FAMILY 22.4 conversions 11 bits wide. The signed decimal format yields 12-bit and 10-bit values, respectively. The sign bit (bit 12 or bit 10) is sign-extended to fill the buffer. The FORM<1:0> bits (AD1CON1<9:8>) select the format. Figure 22-4 and Figure 22-5 show the data output formats that can be selected. Table 22-1 through Table 22-4 show the numerical equivalents for the various conversion result codes.
PIC24FV32KA304 FAMILY TABLE 22-2: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 12-BIT FRACTIONAL FORMATS 16-Bit Fractional Format/ Equivalent Decimal Value 16-Bit Signed Fractional Format/ Equivalent Decimal Value VIN/VREF 12-Bit Output Code +4095/4096 0 1111 1111 1111 1111 1111 1111 0000 0.999 0111 1111 1111 1000 0.999 +4094/4096 0 1111 1111 1110 1111 1111 1110 0000 0.998 0111 1111 1110 1000 0.998 +1/4096 0 0000 0000 0001 0000 0000 0001 0000 0.001 0000 0000 0000 1000 0.
PIC24FV32KA304 FAMILY TABLE 22-4: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 10-BIT FRACTIONAL FORMATS VIN/VREF 10-Bit Differential Output Code (11-bit result) +1023/1024 011 1111 1111 1111 1111 1100 0000 0.999 0111 1111 1110 0000 0.999 +1022/1024 011 1111 1110 1111 1111 1000 0000 0.998 0111 1111 1000 0000 0.998 +1/1024 000 0000 0001 0000 0000 0100 0000 0.001 0000 0000 0010 0000 0.001 0/1024 000 0000 0000 0000 0000 0000 0000 0.000 0000 0000 0000 0000 0.
PIC24FV32KA304 FAMILY 23.0 COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Scalable Comparator Module” (DS39734). The comparator module provides three dual input comparators.
PIC24FV32KA304 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx VIN- COE – VIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CXINB CXINA VIN- Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 01 COE – VIN+ CXINC Cx CxOUT Pin CXINA VIN- COE – VIN+ VBG/2 Cx CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 CXINB CVREF VINVIN+ CVREF VINVIN+ DS30009
PIC24FV32KA304 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 CON bit 15 R/W-0 COE R/W-0 CPOL R/W-0 CLPWR U-0 — U-0 — R/W-0 CEVT R-0 COUT bit 8 R/W-0 EVPOL1 bit 7 R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 R/W-0 CCH0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11-10 bit 9 bit 8 bit 7-6 bit 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CON: Comparator
PIC24FV32KA304 FAMILY REGISTER 23-1: bit 4 bit 3-2 bit 1-0 CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED) CREF: Comparator x Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin Unimplemented: Read as ‘0’ CCH<1:0>: Comparator x Channel Select bits 11 = Inverting input of the comparator connects to VBG 10 = Inverting input of the comparator connects to the CxIND pin 01 = Inverting input of the compa
PIC24FV32KA304 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides a range of output voltages, with 32 distinct levels. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV32KA304 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparat
PIC24FV32KA304 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Charge Time Measurement Unit (CTMU) and CTMU Operation with Threshold Detect” (DS30009743).
PIC24FV32KA304 FAMILY FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse ANx A/D Converter ANy CAPP 25.2 RPR Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s Internal Capacitor (CAD) and a precision resistor for current calibration.
PIC24FV32KA304 FAMILY 25.3 When the voltage on CDELAY equals CVREF, CTPLS goes low. With Comparator 2 configured as the second edge, this stops the CTMU from charging. In this state event, the CTMU automatically connects to ground. The IDISSEN bit doesn’t need to be set and cleared before the next CTPLS cycle. Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock.
PIC24FV32KA304 FAMILY REGISTER 25-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimpl
PIC24FV32KA304 FAMILY REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
PIC24FV32KA304 FAMILY REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED) bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Edge 2 source is Comparator 3 output 1110 = Edge 2 source is Comparator 2 output 1101 = Edge 2 source is Comparator 1 output 1100 = Unimplemented; do not use 1011 = Edge 2 source is IC3 1010 = Edge 2 source is IC2 1001 = Edge 2 source is IC1 1000 = Edge 2 source is CTED13(1) 0111 = Edge 2 source is CTED12(1) 0110 = Edge 2 source is CTED11(1) 0101 = Edge 2 source is CTE
PIC24FV32KA304 FAMILY REGISTER 25-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change fr
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 238 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 26.0 SPECIAL FEATURES Note: 26.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV32KA304 FAMILY REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — GSS0 GWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 GSS0: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled bit 0 GWRP: General Segment Code Flash Write Protec
PIC24FV32KA304 FAMILY REGISTER 26-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 FCKSM1 FCKSM0 R/P-1 R/P-1 R/P-1 R/P-1 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 R/P-1 POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Selection Configuration bits 1x = Clock switching is disabled,
PIC24FV32KA304 FAMILY REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN1 WINDIS FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7,5 FWDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT is enabled in hardware 10 = WDT is controlled with the SWDTEN bit setting
PIC24FV32KA304 FAMILY REGISTER 26-6: R/P-1 (2) MCLRE FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 BORV1(3) BORV0(3) I2C1SEL(1) PWRTEN RETCFG(1) BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(2) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is di
PIC24FV32KA304 FAMILY REGISTER 26-7: R/P-1 DEBUG bit 7 FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — FICD1 FICD0 bit 0 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-2 bit 1-0 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled Unimplemented: Read as ‘0’ FICD
PIC24FV32KA304 FAMILY REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 U-0 DSWDTEN DSBOREN — R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled bit 6 DSBOREN: Deep Sleep/Low-Power BO
PIC24FV32KA304 FAMILY REGISTER 26-9: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bi
PIC24FV32KA304 FAMILY REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 — — — — R R R R REV<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Minor Revision Ide
PIC24FV32KA304 FAMILY 26.2 On-Chip Voltage Regulator All of the PIC24FV32KA304 family devices power their core digital logic at a nominal 3.0V. This may create an issue for designs that are required to operate at a higher typical voltage, as high as 5.0V. To simplify system design, all devices in the “FV” family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is always enabled and provides power to the core from the other VDD pins.
PIC24FV32KA304 FAMILY If the WDT is enabled in hardware (FWDTEN<1:0> = 11), it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bit (RCON<3:2>) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out.
PIC24FV32KA304 FAMILY 26.4 Deep Sleep Watchdog Timer (DSWDT) In PIC24FV32KA304 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled. It is driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWDTOSC (FDS<4>). The DSWDT can be configured to generate a time-out, at 2.1 ms to 25.7 days, by selecting the respective postscaler.
PIC24FV32KA304 FAMILY 27.
PIC24FV32KA304 FAMILY 27.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC24FV32KA304 FAMILY 27.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FV32KA304 FAMILY 27.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC24FV32KA304 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24FV32KA304 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS CALL CLR Assembly Syntax # of Words Description # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C BTST.
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV,
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None REPEAT WDTO, Sleep RESET RESET Software Device Reset 1 1 Non
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 262 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FV32KA304 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FV32KA304 family devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FV32KA304 FAMILY 29.1 DC Characteristics Voltage (VDD) FIGURE 29-1: PIC24FV32KA304 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND EXTENDED) 5.5V 5.5V 3.20V 3.20V 2.00V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 2.0) + 8 MHz. Voltage (VDD) FIGURE 29-2: PIC24F32KA304 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND EXTENDED) 3.60V 3.60V 3.00V 3.00V 1.
PIC24FV32KA304 FAMILY TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristi
PIC24FV32KA304 FAMILY TABLE 29-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol No. DC18 VHLVD Characteristic HLVD Voltage on VDD Transition Min Typ Max Units — — 1.90 V HLVDL<3:0> = 0001 1.86 — 2.13 V HLVDL<3:0> = 0010 2.08 — 2.35 V HLVDL<3:0> = 0011 2.22 — 2.53 V HLVDL<3:0> = 0100 2.30 — 2.
PIC24FV32KA304 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Typical Max Units Conditions 269 450 µA 2.0V IDD Current D20 PIC24FV32KA3XX PIC24F32KA3XX DC22 DC24 DC26 DC30 PIC24FV32KA3XX 465 830 µA 5.0V 200 330 µA 1.8V 410 750 µA 3.3V 490 — µA 2.
PIC24FV32KA304 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Typical Max Units Conditions 120 200 µA 2.0V Idle Current (IIDLE) DC40 DC42 PIC24FV32KA3XX 160 430 µA 5.0V PIC24F32KA3XX 50 100 µA 1.8V 90 370 µA 3.3V PIC24FV32KA3XX 165 — µA 2.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter No. Typical(1) Device Max Units Conditions Power-Down Current (IPD) DC60 PIC24FV32KA3XX 6.0 — 6.0 — PIC24F32KA3XX 0.025 — 0.040 — DC61 DC70 PIC24FV32KA3XX PIC24FV32KA3XX PIC24F32KA3XX — -40°C 8.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter No. Typical(1) Device Max Units 0.50 — µA 0.70 1.5 — 1.5 0.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter No. Typical(1) Device Max Units 0.03 — µA 0.05 0.20 — 0.30 0.03 Conditions Module Differential Current (IPD)(3) DC78 PIC24FV32KA3XX PIC24F32KA3XX DC80 PIC24FV32KA3XX PIC24F32KA3XX -40°C 2.
PIC24FV32KA304 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ(1) Max Units I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C Buffer VSS — 0.
PIC24FV32KA304 FAMILY TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 OSC2/CLKO VOH DO20 Typ(1) Max Units — — 0.4 V IOL = 8.0 mA VDD = 4.5V — — 0.4 V IOL = 4.0 mA VDD = 3.6V — — 0.4 V IOL = 3.5 mA VDD = 2.0V — — 0.4 V IOL = 2.0 mA VDD = 4.5V — — 0.4 V IOL = 1.2 mA VDD = 3.6V — — 0.4 V IOL = 0.4 mA VDD = 2.0V 3.8 — — V IOH = -3.5 mA VDD = 4.5V 3 — — V IOH = -3.0 mA VDD = 3.6V 1.
PIC24FV32KA304 FAMILY TABLE 29-12: DC CHARACTERISTICS: DATA EEPROM MEMORY Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym Min Typ(1) Max Units 100,000 — — E/W VMIN — 3.
PIC24FV32KA304 FAMILY TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +125°C (unless otherwise stated) Param No. Symbol Characteristics Min Typ Max Units Comments DVR10 VBG Band Gap Reference Voltage 0.973 1.024 1.075 V DVR11 TBG Band Gap Reference Start-up Time — 1 — ms DVR20 VRGOUT Regulator Output Voltage 3.1 3.3 3.6 V -40°C < TA < +85°C 3.0 3.19 3.
PIC24FV32KA304 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FV32KA304 family AC characteristics and timing parameters. TABLE 29-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature: -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 29.1 “DC Characteristics”.
PIC24FV32KA304 FAMILY FIGURE 29-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OS30 OS30 Q1 Q2 Q3 OSCI OS20 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 29-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Sym No.
PIC24FV32KA304 FAMILY TABLE 29-20: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FV32KA304 FAMILY FIGURE 29-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 29-3 for load conditions. TABLE 29-23: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.
PIC24FV32KA304 FAMILY TABLE 29-24: COMPARATOR TIMINGS Param No. Symbol Characteristic Min Typ Max Units 300 TRESP Response Time*(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to Output Valid* — — 10 s * Note 1: Comments Parameters are characterized but not tested. Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-25: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param No.
PIC24FV32KA304 FAMILY FIGURE 29-7: BROWN-OUT RESET CHARACTERISTICS Vddcore (Device not in Brown-out Reset) DC15 DC19 (Device in Brown-out Reset) SY25 Reset (Due to BOR) Tvreg + Trst TABLE 29-26: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: AC CHARACTERISTICS Param Symbol No. Operating temperature Characteristic 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.
PIC24FV32KA304 FAMILY FIGURE 29-8: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT TIMING TxCK Pin TtL TtH TtP TABLE 29-27: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT REQUIREMENTS Param. Symbol No.
PIC24FV32KA304 FAMILY FIGURE 29-10: OUTPUT COMPARE x TIMINGS OCx (Output Compare or PWM Mode) OC11 TABLE 29-29: OUTPUT CAPTURE REQUIREMENTS Param. No. Symbol OC11 TCCR OC10 TCCF FIGURE 29-11: OC10 Characteristic OC1 Output Rise Time OC1 Output Fall Time Min Max Units — 10 ns — — ns — 10 ns — — ns Conditions PWM MODULE TIMING REQUIREMENTS OC20 OCFx OC15 PWM TABLE 29-30: PWM TIMING REQUIREMENTS Param. Symbol No.
PIC24FV32KA304 FAMILY I2C BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) FIGURE 29-12: SCLx IM34 IM31 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-3 for load conditions. TABLE 29-31: I2C BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial) -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
PIC24FV32KA304 FAMILY FIGURE 29-13: I2C BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 IM21 SCLx IM10 IM20 IM26 IM25 SDAx In IM45 IM40 SDAx Out Note: Refer to Figure 29-3 for load conditions. TABLE 29-32: I2C BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FV32KA304 FAMILY I2C BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) FIGURE 29-14: IS11 IS21 IS10 SCLx IS25 IS20 IS26 SDAx In IS45 IS40 SDAx Out TABLE 29-33: I2C BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) -40°C TA +125°C (Extended) AC CHARACTERISTICS Param No.
PIC24FV32KA304 FAMILY FIGURE 29-15: I2C BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition TABLE 29-34: I2C BUS START/STOP BITS TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) -40°C TA +125°C (Extended) AC CHARACTERISTICS Param No.
PIC24FV32KA304 FAMILY FIGURE 29-16: UARTx BAUD RATE GENERATOR OUTPUT TIMING UxBRG + 1 * TCY TLW THW UxBCLK TBLD TBHD UxTX FIGURE 29-17: UARTx START BIT EDGE DETECTION UxBRG Any Value Start bit Detected, UxBRG Started TCY Cycle Clock TSETUP TSTDELAY UxRX TABLE 29-35: UARTx TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.
PIC24FV32KA304 FAMILY FIGURE 29-18: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0) SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 TABLE 29-36: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) -40°C TA +125°C (Extended) AC CHARACTERISTICS Param No.
PIC24FV32KA304 FAMILY FIGURE 29-19: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1) SP36 SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 Bit 14 - - - - - -1 MSb SDOx SP40 SDIx LSb SP30,SP31 MSb In Bit 14 - - - -1 LSb In SP41 TABLE 29-37: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.
PIC24FV32KA304 FAMILY FIGURE 29-20: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0) SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 29-38: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.
PIC24FV32KA304 FAMILY FIGURE 29-21: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1) SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIx MSb In LSb In Bit 14 - - - -1 SP41 SP40 TABLE 29-39: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.
PIC24FV32KA304 FAMILY TABLE 29-40: A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply AD05 VREFH Reference Voltage High Greater of: VDD – 0.3 or 1.8 — Lesser of: VDD + 0.3 or 3.
PIC24FV32KA304 FAMILY FIGURE 29-22: A/D CONVERSION TIMING BSET AD1CON1, SAMP BCLR AD1CON1, SAMP (Note 2) AD55 Q3/Q4 AD58 A/D AD59 AD50 CLK(1) A/D DATA 11 10 9 ... ... 2 1 0 OLD DATA ADC1BUFn NEW DATA AD1IF TCY SAMP Note 1: 2: SAMPLING STOPPED If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC24FV32KA304 FAMILY 30.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC24FV32KA304 FAMILY FIGURE 30-3: TYPICAL AND MAXIMUM IIDLE vs. FREQUENCY (EC MODE, 2 MHz TO 32 MHz) 8.0 IIDLE (mA) 7.0 6.0 5.5V Max 5.0 3.3V Max 5.5V Typ 3.3V Typ 4.0 2.5V Max 3.0 2.5V Typ 2.0V Max 2.0 2.0V Typ 1.0 0.0 2 6 10 14 18 22 26 30 Frequency (MHz) FIGURE 30-4: TYPICAL AND MAXIMUM IIDLE vs. FREQUENCY (EC MODE, 1.95 kHz TO 1 MHz) 180 160 5.5V Max IIDLE (µA) 140 5.5V Typ 120 3.3V Max 100 3.3V Typ 2.0V Max 80 2.0V Typ 60 40 0.0 0.2 0.4 0.6 0.8 1.
PIC24FV32KA304 FAMILY FIGURE 30-5: TYPICAL IDD vs. VDD (8 MHZ, EC MODE) 3.5 3.0 IDD (mA) 2.5 -40C 25C 60C 2.0 85C 1.5 1.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-6: TYPICAL IDD vs. VDD (FRC MODE) 3.5 IDD (mA) 3.0 -40 C 25 C 2.5 60 C 85 C 2.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-7: TYPICAL AND MAXIMUM IDD vs. TEMPERATURE (FRC MODE) 3.5 IDD (mA) 3.0 5.5V Max 5.5V Typ 3.3V Max 2.5 3.3V Typ 2.0V Max 2.0V Typ 2.0 1.5 -40 FIGURE 30-8: -15 10 35 Temperature (°C) 60 85 TYPICAL AND MAXIMUM IIDLE vs. VDD (FRC MODE) 1.10 1.00 -40C Typ IDD (mA) -40C Max 0.90 25C Typ 25C Max 60C Typ 0.80 60C Max 85C Typ 0.70 85C Max 0.60 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS30009995E-page 298 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-9: TYPICAL AND MAXIMUM IIDLE vs. TEMPERATURE (FRC MODE) 1.10 1.00 IDD (mA) 5.5V Max 5.5V Typ 0.90 3.3V Max 3.3V Typ 0.80 2.0V Max 2.0V Typ 0.70 0.60 -40 -15 10 35 60 85 Temperature (°C) FIGURE 30-10: FRC FREQUENCY ACCURACY vs. VDD 0.5 Frequency Error (%) 0 -0.5 -40 C 25 C -1 60 C 85 C -1.5 -2 -2.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-11: FRC FREQUENCY ACCURACY vs. TEMPERATURE (2.0V VDD 5.5V) 0.5 0 Frequency Error (%) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -40 FIGURE 30-12: -20 0 20 Temperature (°C) 40 60 80 LPRC FREQUENCY ACCURACY vs. VDD Frequency Error (%) 1 0 -1 -40 C -2 25 C 60 C -3 85 C -4 -5 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS30009995E-page 300 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-13: LPRC FREQUENCY ACCURACY vs. TEMPERATURE (2.0V VDD 5.5V) 1 0 Frequency Error (%) -1 -2 -3 -4 -5 -6 -40 FIGURE 30-14: -20 0 20 Temperature (°C) 40 60 80 TYPICAL AND MAXIMUM IPD vs. VDD 3.5 3.0 -40C Typ 2.5 IPD (µA) -40C Max 25C Typ 2.0 25C Max 60C Typ 1.5 60C Max 85C Typ 1.0 85C Max 0.5 0.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-15: TYPICAL AND MAXIMUM IPD vs. TEMPERATURE 2.0 1.5 5.5V Max IPD (µA) 5.5V Typ 3.3V Max 1.0 3.3V Typ 2.0V Max 2.0V Typ 0.5 0.0 -40 -15 FIGURE 30-16: 10 35 Temperature (°C) 60 85 TYPICAL AND MAXIMUM IPD vs. VDD (DEEP SLEEP MODE) 1500 1250 -40C Typ -40C Max IPD (nA) 1000 25C Typ 25C Max 750 60C Typ 60C Max 500 85C Typ 85C Max 250 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS30009995E-page 302 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-17: TYPICAL AND MAXIMUM IPD vs. TEMPERATURE (DEEP SLEEP MODE) 1500 1250 5.5V Max IPD (nA) 1000 5.5V Typ 3.3V Max 750 3.3V Typ 2.0V Max 500 2.0V Typ 250 0 -40 -15 10 35 60 85 Temperature (°C) FIGURE 30-18: TYPICAL IBOR vs. VDD 10.0 9.0 8.0 IBOR (µA) 7.0 -40 C 6.0 25 C 5.0 60 C 4.0 85 C 3.0 2.0 1.0 0.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-19: TYPICAL IWDT vs. VDD 1.2 1.0 0.8 IWDT (µA) -40C 25C 0.6 60C 85C 0.4 0.2 0.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-20: TYPICAL IDSBOR vs. VDD 25 IDSBOR (nA) 20 -40 C 15 25 C 60 C 10 85 C 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS30009995E-page 304 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-21: TYPICAL IHLVD vs. VDD 10.0 9.0 IHVLD (µA) 8.0 -40C 7.0 25C 60C 6.0 85C 5.0 4.0 3.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-22: TYPICAL IDSWDT vs. VDD 1.4 1.2 IDSWDT (µA) 1.0 85 C 0.8 60 C 25 C 0.6 -40 C 0.4 0.2 0.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-23: TYPICAL VBOR vs. TEMPERATURE (BOR TRIP POINT 3) 1.88 VBOR (V) 1.86 1.84 1.82 1.80 -40 -20 0 20 40 60 80 Temperature (°C) FIGURE 30-24: TYPICAL VOH vs. IOH (GENERAL PURPOSE I/O, AS A FUNCTION OF VDD) 6.0 5.0 VOH (V) 4.0 5.0V 3.0 3.3V 1.8V 2.0 1.0 0.0 0 -5 -10 -15 -20 -25 IOH (mA) DS30009995E-page 306 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-25: TYPICAL VOH vs. IOH (GENERAL PURPOSE I/O, AS A FUNCTION OF TEMPERATURE, 2.0V VDD 5.5V) 3.5 VOH (V) 3.0 -40 C 2.5 25 C 60 C 2.0 85 C 1.5 1.0 0 -5 FIGURE 30-26: -10 -15 IOH (mA) -20 -25 TYPICAL VOL vs. IOL (GENERAL PURPOSE I/O, AS A FUNCTION OF VDD) 1.4 1.2 VOL (V) 1.0 1.8 V 0.8 2.5 V 0.6 3.3 V 5.0 V 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-27: TYPICAL VOL vs. IOL (GENERAL PURPOSE I/O, AS A FUNCTION OF TEMPERATURE, 2.0V VDD 5.5V) 1.2 1.0 VOL (V) 0.8 -40 C 25 C 0.6 60 C 85 C 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) FIGURE 30-28: VIL/VIH vs. VDD (GENERAL PURPOSE I/O, TEMPERATURES AS NOTED) 3.5 3.0 Ensured Logic High VIL/VIH (V) 2.5 VVih IH Typical Typical 2.0 VVIL IL Typical Typical VVIH IH Max -40°C max -40 Indeterminate 1.5 Min85°C 85C IL Min VVIL 1.0 Ensured Logic Low 0.5 0.0 1.5 2.
PIC24FV32KA304 FAMILY VIL/VIH vs. VDD (I2C, TEMPERATURES AS NOTED) FIGURE 30-29: 3.5 3.0 Ensured Logic High VIL/VIH (V) 2.5 VVIH IH Typical Max 85C 2.0 VIH Typical Typical VIL Indeterminate VILMax Typical VIH -40°C 1.5 Min85°C 85C VVIL IL Min 1.0 Ensured Logic Low 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD FIGURE 30-30: VIL/VIH vs. VDD (OSCO, TEMPERATURES AS NOTED) 3.0 2.5 VIL/VIH (V) Ensured Logic High 2.0 VVIH IH Typical Max -40C Indeterminate IL Typical VVIH Typical 1.
PIC24FV32KA304 FAMILY FIGURE 30-31: VIL/VIH vs. VDD (MCLR, TEMPERATURES AS NOTED) 3.0 VIL/VIH (V) 2.5 Ensured Logic High 2.0 VIH Typical VIH Max -40C VIL Typical VIH Typical Indeterminate 1.5 VIL Typical -40°C VIH Max 1.0 VIL Min85°C 85C VIL Min Ensured Logic Low 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD FIGURE 30-32: TYPICAL BAND GAP VOLTAGE vs. VDD 1.035 1.030 -40C 1.025 VBG 25C 60C 1.020 85C 1.015 1.010 2 2.5 3 3.5 4 4.5 5 5.
PIC24FV32KA304 FAMILY TYPICAL BAND GAP VOLTAGE vs. TEMPERATURE (2.0V VDD 5.5V) FIGURE 30-33: 1.04 VBG 1.03 1.02 1.01 1.00 -40 -15 10 35 60 85 Temperature (°C) FIGURE 30-34: TYPICAL VOLTAGE REGULATOR OUTPUT vs. VDD 3.35 3.34 Regulator Output (V) 3.33 3.32 -40 C 3.31 25 C 3.30 60 C 3.29 85 C 3.28 3.27 3.26 3.25 2 2.5 3 3.5 4 4.5 5 5.5 VDD 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-35: TYPICAL VOLTAGE REGULATOR OUTPUT vs. TEMPERATURE 3.35 Regulator Output (V) 3.34 3.33 3.32 3.31 2.0V 3.30 3.3V 3.29 5.5V 3.28 3.27 3.26 3.25 -40 -15 10 35 60 85 Temperature (°C) FIGURE 30-36: HLVD TRIP POINT VOLTAGE vs. TEMPERATURE (HLVDL<3:0> = 0000, PIC24F32KA304 FAMILY DEVICES ONLY 1.90 Average Maximum Minimum Trip Point (V) 1.85 1.80 1.75 1.
PIC24FV32KA304 FAMILY FIGURE 30-37: TEMPERATURE SENSOR DIODE VOLTAGE vs. TEMPERATURE (2.0V VDD 5.5V) 0.90 Diode Voltage (V) 0.85 0.80 0.75 0.70 0.65 0.60 -40 -20 0 20 40 60 80 Temperature (°C) FIGURE 30-38: CTMU OUTPUT CURRENT vs. TEMPERATURE (IRNG<1:0> = 01, 2.0V VDD 5.5V) 0.7 Current (µA) 0.65 0.6 0.55 0.5 -40 -20 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-39: CTMU OUTPUT CURRENT vs. VDD (IRNG<1:0> = 01) 0.70 Current (µA) 0.65 -40 C 25 C 0.60 60 C 85 C 0.55 0.50 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS30009995E-page 314 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 30.2 Note: Characteristics for Extended Temperature Devices (-40°C to +125°C) Data for VDD levels greater than 3.3V are applicable to PIC24FV32KA304 family devices only. TYPICAL AND MAXIMUM IIDLE vs. VDD (FRC MODE) IIDLE (mA) FIGURE 30-40: VDD TYPICAL AND MAXIMUM IIDLE vs. TEMPERATURE (FRC MODE) IIDLE (mA) FIGURE 30-41: Temperature (°C) 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY TYPICAL AND MAXIMUM IPD vs. VDD IPD (µA) FIGURE 30-42: VDD TYPICAL AND MAXIMUM IPD vs. TEMPERATURE IPD (µA) FIGURE 30-43: Temperature (°C) DS30009995E-page 316 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY TYPICAL AND MAXIMUM IPD vs. VDD (DEEP SLEEP MODE) Current (nA) FIGURE 30-44: VDD TYPICAL AND MAXIMUM IPD vs. TEMPERATURE (DEEP SLEEP MODE) Current (nA) FIGURE 30-45: Temperature (°C) 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY TYPICAL IWDT vs. VDD IWDT (µA) FIGURE 30-46: VDD TYPICAL IDSBOR vs. VDD IDSBOR (nA) FIGURE 30-47: VDD DS30009995E-page 318 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY TYPICAL IHLVD vs. VDD IHLVD (µA) FIGURE 30-48: VDD TYPICAL VOL vs. IOL (GENERAL I/O, 2.0V VDD 5.5V) VOL (V) FIGURE 30-49: IOL (MA) 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY TYPICAL VOH vs. IOH (GENERAL I/O, AS A FUNCTION OF TEMPERATURE, 2.0V VDD 5.5V) VOH (V) FIGURE 30-50: - - - - - IOH (mA) FIGURE 30-51: VIL/VIH vs. VDD (GENERAL PURPOSE I/O, TEMPERATURES AS NOTED) VIH Typical VIL Typical Ensured Logic High VIH Max -40°C VIL/VIH (V) VIL Min 125°C Indeterminate Ensured Logic Low VDD DS30009995E-page 320 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-52: VIL/VIH vs. VDD (I2C, TEMPERATURES AS NOTED) VIH Typical Ensured Logic High VIL Typical VIH Max -40°C VIL/VIH (V) VIL Min 125°C Indeterminate Ensured Logic Low VDD FIGURE 30-53: VIL/VIH vs. VDD (OSCO, TEMPERATURES AS NOTED) VIH Typical Ensured Logic High VIL Typical VIH Max -40°C VIL/VIH (V) VIL Min 125°C Indeterminate Ensured Logic Low VDD 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY FIGURE 30-54: VIL/VIH vs. VDD (MCLR, TEMPERATURES AS NOTED) VIH Typical VIL Typical VIH Max -40°C VIL/VIH (V) Ensured Logic High VIL Min 125°C Indeterminate Ensured Logic Low VDD TYPICAL BAND GAP VOLTAGE vs. TEMPERATURE (2.0V VDD 5.5V) VBG (V) FIGURE 30-55: Temperature (°C) DS30009995E-page 322 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY TYPICAL VOLTAGE REGULATOR OUTPUT vs. TEMPERATURE Regulator Output (V) FIGURE 30-56: Temperature (°C) 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 324 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 20-Lead PDIP (300 mil) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SPDIP (.300") PIC24FV32KA301 1710017 Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP (5.30 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN Note: 1710017 Example PIC24FV32KA 301 1710017 28-Lead SSOP (5.
PIC24FV32KA304 FAMILY 20-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC24FV32KA301 1710017 YYWWNNN 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC24FV32KA302 1710017 28-Lead QFN (6x6 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN DS30009995E-page 326 24FV32KA 302 1710017 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 44-Lead QFN (8x8x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC24FV32KA 304 1710017 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 24FV32KA 304 1710017 48-Lead UQFN (6x6x0.5 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 31.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± PLO %RG\ >3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $
PIC24FV32KA304 FAMILY /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 ± PLO %RG\ >63',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ %DVH WR 6HDWLQJ 3ODQH $ ± ± 6KRXOGHU WR 6KRXOGHU :LGWK
PIC24FV32KA304 FAMILY /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK (
PIC24FV32KA304 FAMILY 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.65 0.45 SILK SCREEN c Y1 G X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.65 BSC 7.20 MAX 0.45 1.75 0.20 Notes: 1.
PIC24FV32KA304 FAMILY /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK (
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009995E-page 334 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009995E-page 336 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009995E-page 338 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY DS30009995E-page 340 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS30009995E-page 342 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C C SEATING PLANE A1 A 44X A3 0.08 C SIDE VIEW L 0.10 C A B D2 0.10 C A B E2 K 2 1 NOTE 1 N 44X b 0.07 0.
PIC24FV32KA304 FAMILY 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 6.25 6.25 0.20 0.
PIC24FV32KA304 FAMILY 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC24FV32KA304 FAMILY 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D1 NOTE 2 B (DATUM A) (DATUM B) E1 A NOTE 1 2X 0.20 H A B E A N 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A A2 C SEATING PLANE 0.10 C SIDE VIEW A1 1 2 3 N NOTE 1 44 X b 0.
PIC24FV32KA304 FAMILY 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC24FV32KA304 FAMILY 44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 44 1 2 G C2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X44) X1 Contact Pad Length (X44) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009995E-page 350 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 352 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY APPENDIX A: REVISION HISTORY Revision A (March 2011) Original data sheet for the PIC24FV32KA304 family of devices. Revision B (April 2011) Section 25.0 “Charge Time Measurement Unit (CTMU)” was revised to change the description of the IRNGx bits in CTMUICON (Register 25-3). Setting ‘01’ is the base current level (0.55 A nominal) and setting ‘00’ is 1000x base current. Section 29.
PIC24FV32KA304 FAMILY Revision D (March 2013) For Section 29.0 “Electrical Characteristics”: Throughout the data sheet: corrected the name of RCON register bit 12 as RETEN, to maintain consistency with other PIC24F devices (was previously LVREN). In addition, changed the description of the bit in the RCON register (Register 7-1) to clarify its function in controlling the Retention Regulator.
PIC24FV32KA304 FAMILY INDEX CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ....... 233 CTMU Typical Connections and Internal Configuration for Time Measurement .............. 232 Data Access from Program Space Address Generation ........................................... 52 Data EEPROM Addressing with TBLPAG and NVM Registers .................................................. 65 High/Low-Voltage Detect (HLVD) ............................ 205 I2C Module ......................
PIC24FV32KA304 FAMILY Configuration Bits ............................................................. 239 Core Features .................................................................... 11 CPU ALU ............................................................................ 33 Control Registers ....................................................... 32 Core Registers ........................................................... 30 Programmer’s Model ..................................................
PIC24FV32KA304 FAMILY Input Capture Cascaded (32-Bit) Mode .......................................... 148 Operations ............................................................... 148 Synchronous, Trigger Modes ................................... 147 Input Capture with Dedicated Timers ............................... 147 Instruction Set Opcode Symbols ...................................................... 256 Overview .................................................................. 257 Summary ..........
PIC24FV32KA304 FAMILY Registers AD1CHITH (A/D Scan Compare Hit, High Word) ....................................................... 217 AD1CHITH (A/D Scan Compare Hit, Low Word) ........................................................ 217 AD1CHS (A/D Sample Select) ................................. 216 AD1CON1 (A/D Control 1) ....................................... 211 AD1CON2 (A/D Control 2) ....................................... 212 AD1CON3 (A/D Control 3) .......................................
PIC24FV32KA304 FAMILY RTCC ............................................................................... 185 Alarm Configuration ................................................. 196 Alarm Mask Settings (figure) .................................... 197 Calibration ................................................................ 196 Module Registers ..................................................... 186 Mapping ........................................................... 186 Clock Source Selection ......
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 360 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 362 2011-2017 Microchip Technology Inc.
PIC24FV32KA304 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FV 32 KA3 04 T - I / PT - XXX Examples: a) PIC24FV32KA304-I/ML: Wide voltage range, General Purpose, 32-Kbyte program memory, 44-pin, Industrial temp., QFN package b) PIC24F16KA302-I/SS: Standard voltage range, General Purpose, 16-Kbyte program memory, 28-pin, Industrial temp.
PIC24FV32KA304 FAMILY NOTES: DS30009995E-page 364 2011-2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.
