Datasheet

 2011 Microchip Technology Inc. DS39995B-page 223
PIC24FV32KA304 FAMILY
22.2 A/D Sampling Requirements
The analog input model of the 12-bit A/D Converter is
shown in Figure 22-2. The total sampling time for the
A/D is a function of the holding capacitor charge time.
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD) must be allowed
to fully charge to the voltage level on the analog input
pin. The source impedance (R
S), the interconnect
impedance (R
IC) and the internal sampling switch
(R
SS) impedance combine to directly affect the time
required to charge C
HOLD. The combined impedance of
the analog sources must, therefore, be small enough to
fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage
currents on the accuracy of the A/D Converter, the
maximum recommended source impedance, R
S, is
2.5 k. After the analog input channel is selected
(changed), this sampling function must be completed
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
At least 1 TAD time period should be allowed between
conversions for the sample time. For more details, see
Section 29.0 “Electrical Characteristics”.
EQUATION 22-1: A/D CONVERSION CLOCK
PERIOD
FIGURE 22-2: 12-BIT A/D CONVERTER ANALOG INPUT MODEL
TAD TCY ADCS 1+
ADCS
T
AD
TCY
----------
1–
=
=
Note: Based on TCY = 2/FOSC; Doze mode
and PLL are disabled.
CPIN
VA
Rs
ANx
I
LEAKAGE
RIC  250
Sampling
Switch
R
SS
CHOLD
VSS
= 4.4 pF
500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample-and-Hold Capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  5 k.
R
SS  3 k