Datasheet
2011 Microchip Technology Inc. DS39995B-page 17
PIC24FV32KA304 FAMILY
FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Program Memory
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
PORTA
(1)
RA<0:7>
PORTB
(1)
RB<0:15>
Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-3 for I/O port pin
descriptions.
Comparators
Timer4/5
Timer2/3
CTMU
IC1-3
ADC
12-Bit
PWM/
SPI1
I2C1
CN1-22
(1)
UART1/2
Data EEPROM
OSCI/CLKI
OSCO/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR
FRC/LPRC
Oscillators
DSWDT
Timer1RTCC
REFO
OC1-3
HLVD
PORTC
(1)
RC<9:0>
Precision
Reference
Band Gap
Voltage
V
CAP
Regulator