PIC24FV32KA304 Data Sheet 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC24FV32KA304 FAMILY 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology Power Management Modes: Analog Features: • • • • • • 12-Bit, up to 16-Channel Analog-to-Digital Converter: - 100 ksps conversion rate - Conversion available during Sleep and Idle - Auto-sampling timer-based option for Sleep and Idle modes - Wake on auto-compare option • Dual Rail-to-Rail Analog Comparators with Programmable Input/Output Configuration • On-Chip Voltage Reference • Internal Temperature
PIC24F Device Pins Flash Program (bytes) SRAM (bytes) EE Data (bytes) Timers 16-Bit Capture Input Compare/PWM Output UART w/ IrDA® SPI I2C™ 12-Bit A/D (ch) Comparators CTMU (ch) RTCC PIC24FV32KA304 FAMILY PIC24FV16KA301 /PIC24F16KA301 20 16K 2K 512 5 3 3 2 2 2 12 3 12 Y PIC24FV32KA301 /PIC24F32KA301 20 32K 2K 512 5 3 3 2 2 2 12 3 12 Y PIC24FV16KA302 /PIC24F16KA302 28 16K 2K 512 5 3 3 2 2 2 13 3 13 Y PIC24FV32KA302 /PIC24F32KA302 28 32K 2K 512
PIC24FV32KA304 FAMILY MCLR/RA5 RA0 RA1 RB0 RB1 RB2 RA2 RA3 RB4 RA4 1 2 3 4 5 6 7 8 9 10 24FVXXKA301 20-Pin SPDIP/SSOP/SOIC(1) 24FXXKA301 Pin Diagrams 20 19 18 17 16 15 14 13 12 11 VDD VSS RB15 RB14 RB13 RB12 RA6 OR VCAP RB9 RB8 RB7 Pin Features Pin PIC24FVXXKA301 PIC24FXXKA301 1 MCLR/VPP/RA5 2 PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0 PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0 3 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1 4 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND
PIC24FV32KA304 FAMILY Pin Diagrams MCLR/RA5 RA0 RA1 RB0 RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FVXXKA302 PIC24FXXKA302 28-Pin SPDIP/SSOP/SOIC(1,2) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS RB15 RB14 RB13 RB12 RB11 RB10 RA6 OR VCAP RA7 RB9 RB8 RB7 RB6 Pin Features Pin PIC24FVXXKA302 PIC24FXXKA302 1 MCLR/VPP/RA5 2 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 3 CVREF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1 4 PGED1/
PIC24FV32KA304 FAMILY Pin Diagrams RA1 RA0 MCLR/RA5 VDD VSS RB15 RB14 28-Pin QFN(1,2,3) 28 27 26 25 24 23 22 1 2 3 4 5 6 7 24FVXXKA302 24FXXKA302 8 9 10 11 12 13 14 21 20 19 18 17 16 15 RB13 RB12 RB11 RB10 RA6 OR VCAP RA7 RB9 RB4 RA4 VDD RB5 RB6 RB7 RB8 RB0 RB1 RB2 RB3 VSS RA2 RA3 Pin Features Pin PIC24FVXXKA302 PIC24FXXKA302 1 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 2 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 3 AN4/C1INB/C2IND/SDA2/T5
PIC24FV32KA304 FAMILY Pin Diagrams Pin Features Pin PIC24FVXXKA304 PIC24FVXXKA304 PIC24FXXKA304 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA11 RB14 RB15 VSS VDD MCLR/RA5 RA0 RA1 RB0 RB1 RB9 RC6 RC7 RC8 RC9 RA7 RA6 OR VCAP RB10 RB11 RB12 RB13 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 RB6 RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 44-Pin TQFP/QFN(1,2,3) Legend: Note 1: 2: 3: Pin numbers in bold indicate pin func
PIC24FV32KA304 FAMILY Pin Diagrams Pin Features Pin 48-Pin UQFN(1,2,3) SDA1/T1CK/U1RTS/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/CTED4/CN21/ RB9 2 U1RX/CN18/RC6 U1RX/CN18/RC6 RB8 RB7 RB6 RB5 n/c VDD VSS RC5 RC4 RC3 RA9 RA4 3 U1TX/CN17/RC7 U1TX/CN17/RC7 4 OC2/CN20/RC8 OC2/CN20/RC8 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 5 IC2/CTED7/CN19/RC9 IC2/CTED7/CN19/RC9 6 IC1/CTED3/CN9/RA7 IC1/CTED3/CN9/RA7 7 VCAP INT2/RA6 8 n/c n/c 9 PGED2/SDI1/CTED11/CN16/RB10 PGED2/SDI1/CTED
PIC24FV32KA304 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 25 3.0 CPU ....................................................................................................
PIC24FV32KA304 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 12 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • • • PIC24FV16KA301, PIC24F16KA301 PIC24FV16KA302, PIC24F16KA302 PIC24FV16KA304, PIC24F16KA304 PIC24FV32KA301, PIC24F32KA301 PIC24FV32KA302, PIC24F32KA302 PIC24FV32KA304, PIC24F32KA304 The PIC24FV32KA304 family introduces a new line of extreme low-power Microchip devices.
PIC24FV32KA304 FAMILY The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.
PIC24FV32KA304 FAMILY PIC24FV32KA302 PIC24FV16KA304 PIC24FV32KA304 Program Memory (bytes) 16K 32K 16K 32K 16K 32K Program Memory (instructions) 5632 11264 5632 11264 5632 11264 Features Operating Frequency PIC24FV16KA302 PIC24FV32KA301 DEVICE FEATURES FOR THE PIC24FV32KA304 FAMILY PIC24FV16KA301 TABLE 1-1: DC – 32 MHz Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/ NMI traps) 30 (26/4) I/O Ports Total I/O Pins PORTA<5:0> PORTB<15:12,9:
PIC24FV32KA304 FAMILY Operating Frequency PIC24F32KA304 PIC16F16KA304 PIC24F32KA302 PIC24F16KA302 Features PIC24F32KA301 DEVICE FEATURES FOR THE PIC24F32KA304 FAMILY PIC24F16KA301 TABLE 1-2: DC – 32 MHz Program Memory (bytes) 16K 32K 16K 32K 16K 32K Program Memory (instructions) 5632 11264 5632 11264 5632 11264 Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/ NMI traps) 30 (26/4) I/O Ports Total I/O Pins PORTA<6:0>, PORTB<15:12, 9:7, 4
PIC24FV32KA304 FAMILY FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller 16 16 16 8 Data Latch PSV and Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTA(1) RA<0:7> 16 23 16 Read AGU Write AGU Address Latch Program Memory PORTB(1) Data EEPROM RB<0:15> Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTC(1) RC<9:0> Inst Register Instruction Decode and
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS F FV Pin Number Pin Number Function 28-Pin SPDIP/ SSOP/ SOIC I/O Buffer 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN AN0 2 19 2 27 19 21 2 19 2 27 19 21 I ANA AN1 3 20 3 28 20 22 3 20 3 28 20 22 I ANA AN2 4 1 4 1 21 23 4 1 4 1 21 23 I ANA AN3 5 2 5 2 22 24 5 2 5 2 22 24 I ANA AN4 6 3 6 3 23 25 6 3 6 3 23 25 I ANA AN5 — — 7 4 24 26 — — 7 4 24 26 I ANA AN6 — — — — 25 27 —
2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number Function 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN CN18 — — — — 2 2 — CN19 –- –- — — 5 5 — 28-Pin SPDIP/SSOP/ SOIC 28-Pin QFN 44-Pin QFN/TQFP 48-Pin UQFN 20-Pin PDIP/SSOP/ SOIC I/O Buffer 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN — — — 2 2 I ST — — –- 5 5 I ST 20-Pin QFN 44-Pin QFN/TQFP Description 48-Pin UQFN CN20 –- –- — — 4 4 — — –- –- 4 4 I ST CN21 13 10 18 15 1 1 13
2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number Function 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN PGED2 3 PGEC3 10 PGED3 28-Pin SPDIP/SSOP/ SOIC 28-Pin QFN 20 21,3 18,28 8,20 7 12,15 9,12 34,42 9 6 11,14 8,11 33,41 RA0 2 19 2 27 RA1 3 20 3 28 I/O Buffer 9,22 I/O ST 37,46 I/O ST ICSP Clock 3 36,45 I/O ST ICSP Data 3 19 21 I/O ST PORTA Pins 20 22 I/O ST ST 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 20 21,3 18,28 8,20 7 12,15
2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number Function 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN T5CK 6 3 U1CTS 12 9 U1RTS 13 10 18 U1RX 6 3 U1TX 11 8 U2CTS 10 7 12 9 U2RTS 9 6 11 8 U2RX 5 2 5 2 U2TX 4 1 4 1 ULPWU 4 1 4 1 28-Pin SPDIP/SSOP/ SOIC 20-Pin PDIP/SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC I/O Buffer 25 I ST Timer5 Clock 48 I ST UART1 Clear to Send Input O — UART1 Request to Send Output 2,25 I ST UART1 Receive 3
PIC24FV32KA304 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VCAP pins (see Section 2.
PIC24FV32KA304 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24FV32KA304 FAMILY Voltage Regulator Pin (VCAP) Note: This section applies only to PIC24F K devices with an on-chip voltage regulator. Refer to Section 29.0 “Electrical Characteristics” for information on VDD and VDDCORE. FIGURE 2-3: Some of the PIC24F K devices have an internal voltage regulator. These devices have the voltage regulator output brought out on the VCAP pin.
PIC24FV32KA304 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PIC24FV32KA304 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to for Section 9.0 “Oscillator Configuration”details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 30 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the “PIC24F Family Reference Manual”, Section 2. “CPU” (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24FV32KA304 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory Data EEPROM EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support Literal Data 16 1
PIC24FV32KA304 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL RA N OV Z C 2 1 0 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Regi
PIC24FV32KA304 FAMILY 3.
PIC24FV32KA304 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(1) PSV — — bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1
PIC24FV32KA304 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24FV32KA304 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and bussing. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh).
PIC24FV32KA304 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In the PIC24FV32KA304 family, the data EEPROM is mapped to the top of the user program memory space, starting at address, 7FFE00, and expanding up to address, 7FFFFF. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented.
PIC24FV32KA304 FAMILY 4.2 PIC24FV32KA304 family devices implement a total of 1024 words of data memory. If an EA points to a location outside of this area, an all zero word or byte will be returned. Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 4-3. 4.2.
PIC24FV32KA304 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations.
File Name Start Addr CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 WREG0 0000 WREG1 0002 WREG1 0000 WREG2 0004 WREG2 0000 WREG3 0006 WREG3 0000 WREG4 0008 WREG4 0000 WREG5 000A WREG5 0000 WREG6 000C WREG6 0000 WREG7 000E WREG7 0000 WREG8 0010 WREG8 0000 WREG9 0012 WREG9 0000 WREG10 0014 WREG10 0000 WREG11 0016 WREG11 0000 WREG12 0018 WREG12
2011 Microchip Technology Inc.
File Name Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 All Resets 0000 — — — — — — — — — — STKERR OSCFAIL — INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF — OC3IF — — — —
2011 Microchip Technology Inc.
OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 OC1CON1 0190 — — OCSIDL OC1CON2 0192 FLTMD FLTOUT FLTTRIEN Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCINV — DCB1 DCB0 OC32 Bit 6 Bit 5 OCFLT2 OCFLT1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC1RS 0194 OC1RS 0000 OC1R 0196 OC1R 0000 OC1TMR 0198 OC2C
2011 Microchip Technology Inc.
File Name SPI REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 SPI1STAT 0240 SPIEN — SPISIDL — — SRMPT SPIROV SR1MPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 SPI1BUF 0248 SPI2STAT 0
2011 Microchip Technology Inc.
File Name Addr ADC REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ADC1BUF0 0300 ADC1BUF0 xxxx ADC1BUF1 0302 ADC1BUF1 xxxx ADC1BUF2 0304 ADC1BUF2 xxxx ADC1BUF3 0306 ADC1BUF3 xxxx ADC1BUF4 0308 ADC1BUF4 xxxx ADC1BUF5 030A ADC1BUF5 xxxx ADC1BUF6 030C ADC1BUF6 xxxx ADC1BUF7 030E ADC1BUF7 xxxx ADC1BUF8 0310 ADC1BUF8 xxxx ADC1BUF9 0312 ADC1BUF9 xxxx ADC1BUF10 0314 ADC1BUF10 x
2011 Microchip Technology Inc.
File Name CRC REGISTER MAP Addr Bit 15 Bit 14 Bit 13 CRCCON1 0640 CRCEN — CSIDL CRCCON2 0642 — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 Bit 1 Bit 0 All Resets — — — 0000 PLEN2 PLEN1 PLEN0 0000 0000 CRCXORL 0644 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 — CRCXORH 0646 X31 X30
2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24FV32KA304 FAMILY TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0>(2) Data EA<14:
PIC24FV32KA304 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. It also offers a direct method of reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.
PIC24FV32KA304 FAMILY In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space.
PIC24FV32KA304 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into an 16K word page (in PIC24FV16KA3XX devices) and a 32K word page (in PIC24FV32KA3XX devices) of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 58 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Flash programming, refer to the “PIC24F Family Reference Manual”, Section 4. “Program Memory” (DS39715). The PIC24FV32KA304 of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with VDD over 1.8V.
PIC24FV32KA304 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time and to program one row at a time. It is also possible to program single words. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks and single row write block (96 bytes) are edge-aligned, from the beginning of program memory.
PIC24FV32KA304 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY(4) — — — — bit 15 U-0 — bit 8 R/W-0 ERASE R/W-0 NVMOP5 R/W-0 (1) R/W-0 (1) R/W-0 (1) NVMOP4 NVMOP3 NVMOP2 R/W-0 (1) NVMOP1 R/W-0 (1) NVMOP0(1) bit 7 bit 0 SO = Settable Only bit Legend: HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, re
PIC24FV32KA304 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is as follows: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOP bits (NVMCON<5:0>) to ‘011000’ to configure for row erase.
PIC24FV32KA304 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE // C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = &progAddr;// Global variable located in Pgm Memory unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); offset = &progAddr & 0xFFFF; // Initialize PM Page Boundary SFR // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // wi
PIC24FV32KA304 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr = &progAddr;// Global variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write //Set up NVMCON for row programming NVMCON = 0x4001; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = __buil
PIC24FV32KA304 FAMILY EXAMPLE 5-7: ; Setup MOV MOV MOV MOV MOV TBLWTL TBLWTH ; Setup MOV MOV DISI MOV MOV MOV MOV BSET PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY a pointer to data Program Memory #tblpage(PROG_ADDR), W0 ; W0, TBLPAG ;Initialize PM Page Boundary SFR #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address #LOW_WORD_N, W2 ; #HIGH_BYTE_N, W3 ; W2, [W0] ; Write PM low word into program latch W3, [W0++] ; Write PM high byte into program latch NVMCON for programming on
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 66 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 6.0 Note: DATA EEPROM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Data EEPROM, refer to the “PIC24F Family Reference Manual”, Section 5. “Data EEPROM” (DS39720). The data EEPROM memory is a Nonvolatile Memory (NVM), separate from the program and volatile data RAM.
PIC24FV32KA304 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 bit 7 bit 0 Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is u
PIC24FV32KA304 FAMILY 6.3 NVM Address Register As with Flash program memory, the NVM Address Registers, NVMADRU and NVMADR, form the 24-bit Effective Address (EA) of the selected row or word for data EEPROM operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA.
PIC24FV32KA304 FAMILY 6.4.1 ERASE DATA EEPROM A typical erase sequence is provided in Example 6-2. This example shows how to do a one-word erase. Similarly, a four-word erase and an eight-word erase can be done. This example uses C library procedures to manage the Table Pointer (builtin_tblpage and builtin_tbloffset) and the Erase Page Pointer (builtin_tblwtl). The memory unlock sequence (builtin_write_NVM) also sets the WR bit to initiate the operation and returns control when complete.
PIC24FV32KA304 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the address registers do not need to be configured because this operation affects the entire data EEPROM. The following sequence helps in performing a bulk erase: To write a single word in the data EEPROM, the following sequence must be followed: 1. 2. 2. 3. 4. 5. Configure NVMCON to Bulk Erase mode. Clear NVMIF status bit and enable NVM interrupt (optional).
PIC24FV32KA304 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the table read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location followed by a TBLRDL instruction.
PIC24FV32KA304 FAMILY 7.0 RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Resets, refer to the “PIC24F Family Reference Manual”, Section 40. “Reset with Programmable Brown-out Reset” (DS39728). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24FV32KA304 FAMILY REGISTER 7-1: R/W-0, HS TRAPR bit 15 R/W-0, HS EXTR bit 7 R/W-0, HS R/W-0 R/W-0 U-0 R/C-0, HS R/W-0 IOPUWR SBOREN LVREN(3) — DPSLP CM R/W-0, HS SWR R/W-0, HS SWDTEN(2) R/W-0, HS WDTO R/W-0, HS SLEEP R/W-0, HS IDLE R/W-1, HS BOR Legend: R = Readable bit -n = Value at POR bit 15 RCON: RESET CONTROL REGISTER(1) C = Clearable bit W = Writable bit ‘1’ = Bit is set R/W-0 PMSLP bit 8 R/W-1, HS POR bit 0 HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ =
PIC24FV32KA304 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 7-1: bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-
PIC24FV32KA304 FAMILY 7.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 7-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.
PIC24FV32KA304 FAMILY 7.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24FV32KA304 FAMILY 7.5.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘0’ in the software immediately after any POR event.
PIC24FV32KA304 FAMILY 8.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU.
PIC24FV32KA304 FAMILY Decreasing Natural Order Priority FIGURE 8-1: Note 1: DS39995B-page 80 PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap V
PIC24FV32KA304 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error Reserved 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source ADC1 Conversion Done Vector Number IVT Address 13 00002Eh Interrupt Bit
PIC24FV32KA304 FAMILY 8.3 Interrupt Control and Status Registers The PIC24FV32KA304 family of devices implements a total of 22 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0, IFS1, IFS3 and IFS4 IEC0, IEC1, IEC3 and IEC4 IPC0 through IPC5, IPC7 and IPC15 through IPC19 • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2.
PIC24FV32KA304 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC IPL2 R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) (2,3) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9
PIC24FV32KA304 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 R/C-0, HSC (2) — IPL3 R/W-0 U-0 U-0 — — (1) PSV bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Pri
PIC24FV32KA304 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interru
PIC24FV32KA304 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = U
PIC24FV32KA304 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS NVMIF bit 15 U-0 — R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF R/W-0, HS SPI1IF R/W-0, HS SPF1IF R/W-0, HS T3IF bit 8 R/W-0, HS T2IF bit 7 R/W-0, HS OC2IF R/W-0, HS IC2IF U-0 — R/W-0, HS T1IF R/W-0, HS OC1IF R/W-0, HS IC1IF R/W-0, HS INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 HS = Hardwa
PIC24FV32KA304 FAMILY REGISTER 8-5: bit 1 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS U2TXIF bit 15 R/W-0, HS U2RXIF U-0 — U-0 — R/W-0, HS INT2IF R/W-0, HS T5IF R/W-0, HS T4I
PIC24FV32KA304 FAMILY REGISTER 8-6: bit 1 IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0, HS U
PIC24FV32KA304 FAMILY REGISTER 8-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS U-0 — — — — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calen
PIC24FV32KA304 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: C
PIC24FV32KA304 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — ULPWUIF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Stat
PIC24FV32KA304 FAMILY REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 NVMIE bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read
PIC24FV32KA304 FAMILY REGISTER 8-11: bit 1 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 REGISTER 8-12: R/W-0 U2TXIE bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2RXIE R/W-0 INT2IE R/W-0 T5IE R/W-0 T4IE U-0 — U-0 — R/W-0 INT1IE R/W-0 CNIE bit 7 Legend:
PIC24FV32KA304 FAMILY REGISTER 8-12: bit 1 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
PIC24FV32KA304 FAMILY REGISTER 8-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrup
PIC24FV32KA304 FAMILY REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt reques
PIC24FV32KA304 FAMILY REGISTER 8-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ULPWUIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Bit 1 = Interrupt request is ena
PIC24FV32KA304 FAMILY REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1
PIC24FV32KA304 FAMILY REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrup
PIC24FV32KA304 FAMILY REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FV32KA304 FAMILY REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Inte
PIC24FV32KA304 FAMILY REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CN
PIC24FV32KA304 FAMILY REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrup
PIC24FV32KA304 FAMILY REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T4IP2 T4IP1 T4IP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 =
PIC24FV32KA304 FAMILY REGISTER 8-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FV32KA304 FAMILY REGISTER 8-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Prio
PIC24FV32KA304 FAMILY REGISTER 8-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Event Interrupt Priority bits
PIC24FV32KA304 FAMILY REGISTER 8-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP <2:0>: Master I2C2 E
PIC24FV32KA304 FAMILY REGISTER 8-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority b
PIC24FV32KA304 FAMILY REGISTER 8-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC
PIC24FV32KA304 FAMILY REGISTER 8-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
PIC24FV32KA304 FAMILY REGISTER 8-32: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — ULPWUIP2 ULPWUIP1 ULPWUIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 6-4 ULPWUIP<2:0>: Ultra Low-Power Wake-up Interrupt Priority
PIC24FV32KA304 FAMILY REGISTER 8-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interr
PIC24FV32KA304 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 116 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 9.0 • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode. When using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown.
PIC24FV32KA304 FAMILY 9.1 CPU Clocking Scheme 9.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24FV32KA304 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit.
PIC24FV32KA304 FAMILY 9.3 The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): The FRC Oscillator Tune register (Register 9-3) allows the user to fine tune the FRC oscillator over a range of approximately ±5.25%.
PIC24FV32KA304 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24FV32KA304 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit, a
PIC24FV32KA304 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111
PIC24FV32KA304 FAMILY 9.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 9.4.1 The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits.
PIC24FV32KA304 FAMILY The following code sequence for a clock switch is recommended: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24FV32KA304 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Referenc
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 126 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 10.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 39. Power-Saving Features with Deep Sleep” (DS39727). The PIC24FV32KA304 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24FV32KA304 FAMILY 10.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.6 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24FV32KA304 FAMILY 10.2.4.2 Exiting Deep Sleep Mode Deep Sleep mode exits on any one of the following events: • POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. • DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. • RTCC alarm (if RTCEN = 1). • Assertion (‘0’) of the MCLR pin.
PIC24FV32KA304 FAMILY 10.2.4.5 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWCKSEL Configuration bit (FDS<4>). The postscaler options are programmed by the DSWDTPS<3:0> Configuration bits (FDS<3:0>). The minimum time-out period that can be achieved is 2.
PIC24FV32KA304 FAMILY DSCON: DEEP SLEEP CONTROL REGISTER(1) REGISTER 10-1: R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 DSEN — — — — — — RTCCWDIS bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — U-0 — R/W-0 ULPWUDIS R/W-0 R/C-0, HS (2) DSBOR RELEASE bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enab
PIC24FV32KA304 FAMILY DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) REGISTER 10-2: U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR(2,3) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimp
PIC24FV32KA304 FAMILY 10.3 Ultra Low-Power Wake-up EXAMPLE 10-3: ULTRA LOW-POWER WAKE-UP INITIALIZATION The Ultra Low-Power Wake-up (ULPWU) on pin, RB0, allows a slow falling voltage to generate an interrupt without excess current consumption. //******************************* To use this feature: //******************************* 1. 2. 3. 4. 5. Charge the capacitor on RB0 by configuring the RB0 pin to an output and setting it to ‘1’. Stop charging the capacitor by configuring RB0 as an input.
PIC24FV32KA304 FAMILY ULPWCON: ULPWU CONTROL REGISTER(1) REGISTER 10-3: R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 ULPEN — ULPSIDL — — — — ULPSINK bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ULPEN: ULPWU Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’
PIC24FV32KA304 FAMILY 10.4 Voltage Regulator-Based Power-Saving Features PIC24FV32KA304 series devices have a voltage regulator that has the ability to alter functionality to provide power savings. The on board regulator is made up of two basic modules: the High-Voltage Regulator (HVREG) and the Low-Voltage Regulator (LVREG). With the combination of HVREG and LVREG, the following power modes are available: 10.4.
PIC24FV32KA304 FAMILY TABLE 10-1: VOLTAGE REGULATION CONFIGURATION SETTINGS FOR PIC24FV32KA304 DEVICES LVRCFG bit (FPOR<2>) LVREN bit (RCON<12> PMSLP bit (RCON<8>) 0 0 1 0 0 0 Power Mode During Sleep Fast Wake-up HVREG mode (normal) is unchanged during Sleep Sleep LVREG is unused Sleep HVREG goes to Low-Power Standby mode during Sleep (Standby) 0 1 0 Low Voltage Sleep 1 1 X X 1 0 LVREG is unused HVREG is off during Sleep LVREG is enabled and provides Sleep voltage regulation Fast Wak
PIC24FV32KA304 FAMILY 10.5 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 138 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 11.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O Ports, refer to the “PIC24F Family Reference Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24FV32KA304 family devices do not support Peripheral Pin Select features.
PIC24FV32KA304 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 11.
PIC24FV32KA304 FAMILY REGISTER 11-2: ANSB: ANALOG SELECTION (PORTB) R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 ANSB15 ANSB14 ANSB13 ANSB12 — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — ANSB4 ANSB3(1) ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 ANSB<15:12>: Analog Select Control
PIC24FV32KA304 FAMILY 11.2.2 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 11.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FV32KA304 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins.
PIC24FV32KA304 FAMILY 12.0 Note: Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. TIMER1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3. 4.
PIC24FV32KA304 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON — TSIDL — — — T1ECS1(1) T1ECS0(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 U
PIC24FV32KA304 FAMILY 13.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent,16-bit timers with selectable operating modes.
PIC24FV32KA304 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE TGATE TCS Q 1 Set T3IF (T5IF) Q 0 PR3 (PR5) ADC Event Trigger(2) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4) (1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operatio
PIC24FV32KA304 FAMILY FIGURE 13-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TGATE TMR2 (TMR4) Sync Comparator PR2 (PR4) FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) Sync 1x TON Prescaler 1, 8, 64, 256 01 00 TGATE TCY Set T3IF (T5IF) TCKPS<1:0> 2 1 0 Reset ADC Event Trigger(1) Equal Q D Q CK TCS TGATE
PIC24FV32KA304 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 R/W-0 T32 (1) U-0 R/W-0 U-0 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer2 On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timer
PIC24FV32KA304 FAMILY REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 150 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 14.0 INPUT CAPTURE WITH DEDICATED TIMERS 14.1 14.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 34. “Input Capture with Dedicated Timer” (DS39722). Note: All devices in the PIC24FV32KA304 family features 3 independent input capture modules.
PIC24FV32KA304 FAMILY 14.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd-numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (ICy) provides the Most Significant 16 bits.
PIC24FV32KA304 FAMILY REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 — R/W-0 ICI1 ICI0 R-0, HCS R-0, HCS R/W-0 R/W-0 R/W-0 ICBNE ICM2(1) ICM1(1) ICM0(1) ICOV bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
PIC24FV32KA304 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unim
PIC24FV32KA304 FAMILY 15.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 35. “Output Compare with Dedicated Timer” (DS39723). All devices in the PIC24FV32KA304 family feature 3 independent output compare modules.
PIC24FV32KA304 FAMILY FIGURE 15-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) DCBx OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLTx OCFLTx OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OC Clock Sources Clock Select OCxCON2 OCxR Increment Comparator OC Output and Fault Logic OCxTMR Reset Trigger and Sync Sources Match Event Trigger and Sync Logic Comparator OCx Pin Match Event Match Event OCFA/ OCFB/ CxOUT OCxRS Reset OCx Interrupt DS39995B-page 156 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 15.2 Compare Operations In Compare mode (Figure 15-1), the output compare module can be configured for single-shot or continuous pulse generation. It can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. 3. 4. 5. 6. Calculate the required values for the OCxR and (for Double Compare modes) OCxRS Duty Cycle registers: a) Determine the instruction clock cycle time.
PIC24FV32KA304 FAMILY 15.3 4. Pulse-Width Modulation (PWM) Mode 5. In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare edge-aligned PWM operation: 1. 2. 3. module 6. 7. for Select a clock source by writing the OCTSEL2<2:0> (OCxCON<12:10>) bits.
PIC24FV32KA304 FAMILY 15.3.1 PWM PERIOD 15.3.2 PWM DUTY CYCLE In Edge-Aligned PWM mode, the period is specified by the value of the OCxRS register. In Center-Aligned PWM mode, the period of the synchronization source, such as the Timers’ PRy, specifies the period. The period in both cases can be calculated using Equation 15-1. The PWM duty cycle is specified by writing to the OCxRS and OCxR registers.
PIC24FV32KA304 FAMILY 15.4 The DCB bits are intended for use with a clock source identical to the system clock. When an OCx module with enabled prescaler is used, the falling edge delay caused by the DCB bits will be referenced to the system clock period rather than the OCx module’s period. Subcycle Resolution The DCB bits (OCxCON2<10:9>) provide for resolution better than one instruction cycle. When used, they delay the falling edge generated from a match event by a portion of an instruction cycle.
PIC24FV32KA304 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 bit 15 R/W-0 bit 8 R/W-0, HCS ENFLT0 R/W-0, HCS OCFLT2 R/W-0, HCS OCFLT1 OCFLT0 R/W-0 TRIGMODE R/W-0 (1) OCM2 R/W-0 OCM1 (1) R/W-0 OCM0(1) bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is
PIC24FV32KA304 FAMILY REGISTER 15-1: bit 2-0 Note 1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx 110 = Edge-Aligned PWM mode on OCx 101 = Double Compare Continuous Pulse mode: initialize OCx pin low, toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: initialize OCx pin low, toggle OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare
PIC24FV32KA304 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1(3) DCB0(3) OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’
PIC24FV32KA304 FAMILY REGISTER 15-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Reserved 11101 = Reserved 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 100xx = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2
PIC24FV32KA304 FAMILY 16.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Serial Peripheral Interface, refer to the “PIC24F Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” (DS39699).
PIC24FV32KA304 FAMILY FIGURE 16-1: SPIx MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 1:1 to 1:8 Secondary Prescaler SS1/FSYNC1 Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPI1CON1<1:0> SPI1CON1<4:2> Shift Control SDO1 Enable Master Clock bit 0 SDI1 FCY SPI1SR Transfer Transfer SPI1BUF Read SPI1BUF Write SPI1BUF 16 Internal Data Bus DS39995B-page 166 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY To set up the SPI1 module for the Enhanced Buffer Master (EBM) mode of operation: To set up the SPI1 module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register. b) Set the respective SPI1IE bit in the IEC0 register. c) Write the respective SPI1IPx bits in the IPC2 register. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 1.
PIC24FV32KA304 FAMILY REGISTER 16-1: R/W-0 SPIEN bit 15 R-0,HSC SRMPT bit 7 U-0 — bit 14 bit 13 bit 12-11 bit 10-8 bit 7 bit 6 bit 5 bit 4-2 R/W-0 SPISIDL U-0 — U-0 — R-0, HSC SPIBEC2 R-0, HSC SPIBEC1 R-0, HSC SPIBEC0 bit 8 R/C-0, HS R/W-0, HSC SPIROV SRXMPT R/W-0 SISEL2 R/W-0 SISEL1 R/W-0 SISEL0 R-0, HSC SPITBF R-0, HSC SPIRBF bit 0 Legend: R = Readable bit -n = Value at POR bit 15 SPIxSTAT: SPIx STATUS AND CONTROL REGISTER C = Clearable bit W = Writable bit ‘1’ = Bit is set HS = Har
PIC24FV32KA304 FAMILY REGISTER 16-1: bit 1 bit 0 SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) SPITBF: SPI1 Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
PIC24FV32KA304 FAMILY REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 — bit 15 U-0 — U-0 — R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 SSEN bit 7 R/W-0 CKP R/W-0 MSTEN R/W-0 SPRE2 R/W-0 SPRE1 R/W-0 SPRE0 R/W-0 PPRE1 R/W-0 PPRE0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x =
PIC24FV32KA304 FAMILY REGISTER 16-2: bit 1-0 Note 1: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).
PIC24FV32KA304 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PIC24FV32KA304 FAMILY 17.0 Note: INTER-INTEGRATED CIRCUIT™ (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Inter-Integrated Circuit, refer to the “PIC24F Family Reference Manual”, Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS39702). 17.2 The details of sending a message in Master mode depends on the communications protocol for the device being communicated with.
PIC24FV32KA304 FAMILY FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2C1RCV SCL1 Read Shift Clock I2C1RSR LSB SDA1 Address Match Match Detect Write I2C1MSK Write Read I2C1ADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2C1STAT Collision Detect Read Write I2C1CON Acknowledge Generation Read Clock Stretching Write I2C1TRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2C1BRG Read TCY/2 DS39995B-page 174 2011 Microchip Technol
PIC24FV32KA304 FAMILY 17.3 Setting Baud Rate When Operating as a Bus Master 17.4 The I2C1MSK register (Register 17-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2C1MSK register causes the slave module to respond, whether the corresponding address bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set to ‘00100000’, the slave module will detect both addresses: ‘0000000’ and ‘00100000’.
PIC24FV32KA304 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
PIC24FV32KA304 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
PIC24FV32KA304 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC IWCOL I2COV D/A P R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value a
PIC24FV32KA304 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop detected.
PIC24FV32KA304 FAMILY REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AM
PIC24FV32KA304 FAMILY 18.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Universal Asynchronous Receiver Transmitter, refer to the “PIC24F Family Reference Manual”, Section 21. “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in this PIC24F device family.
PIC24FV32KA304 FAMILY 18.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. Equation 18-1 provides the formula for computation of the baud rate with BRGH = 0. EQUATION 18-1: Baud Rate = The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536).
PIC24FV32KA304 FAMILY 18.2 1. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of UxTXREG word.
PIC24FV32KA304 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2) UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FV32KA304 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1
PIC24FV32KA304 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 HC = Hardware Clearable bit Legend: HS = Hardware Settable bit C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writa
PIC24FV32KA304 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the t
PIC24FV32KA304 FAMILY REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER U-x — bit 15 U-x — U-x — U-x — U-x — U-x — U-x — W-x UTX8 bit 8 W-x UTX7 bit 7 W-x UTX6 W-x UTX5 W-x UTX4 W-x UTX3 W-x UTX2 W-x UTX1 W-x UTX0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 bit 7-0 U-0 — bit 15 UxRXREG: UARTx RECEIVE REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0, HSC URX8 bit 8 R-0, HSC URX6 R-0, HSC URX5 R-0, HSC URX4 R-0, HSC URX3 R-0, HSC URX2 R-0, HSC URX1 R-0, HSC U
PIC24FV32KA304 FAMILY 19.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Real-Time Clock and Calendar, refer to the “PIC24F Family Reference Manual”, Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696). The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated.
PIC24FV32KA304 FAMILY 19.2 RTCC Module Registers TABLE 19-2: The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.2.1 To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 19-1).
PIC24FV32KA304 FAMILY 19.2.
PIC24FV32KA304 FAMILY REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute . . .
PIC24FV32KA304 FAMILY REGISTER 19-2: R/W-0 PWCEN RTCPWC: RTCC CONFIGURATION REGISTER 2(1) R/W-0 PWCPOL R/W-0 PWCCPRE R/W-0 PWCSPRE R/W-0 (2) RTCCLK1 R/W-0 R/W-0 R/W-0 RTCCLK0(2) RTCOUT1 RTCOUT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWCEN: Power Control Enable bit 1 = Power con
PIC24FV32KA304 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 ALRMEN bit 15 R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ARPT7 bit 7 R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9-8 bit 7-0 W = Writable bit ‘1’ = Bit is set R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is u
PIC24FV32KA304 FAMILY 19.2.
PIC24FV32KA304 FAMILY REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY
PIC24FV32KA304 FAMILY 19.2.
PIC24FV32KA304 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
PIC24FV32KA304 FAMILY REGISTER 19-11: RTCCSWT: CONTROL/SAMPLE WINDOW TIMER REGISTER(1) R/W-x PWCSTAB7 bit 15 R/W-x PWCSTAB6 R/W-x PWCSTAB5 R/W-x PWCSTAB4 R/W-x PWCSTAB3 R/W-x PWCSTAB2 R/W-x PWCSTAB1 R/W-x PWCSTAB0 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSAMP7 PWCSAMP6 PWCSAMP5 PWCSAMP4 PWCSAMP3 PWCSAMP2 PWCSAMP1 PWCSAMP0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit
PIC24FV32KA304 FAMILY 19.3 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will be either added or subtracted from the RTCC timer, once every minute.
PIC24FV32KA304 FAMILY FIGURE 19-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s m s s m m s s 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week d 1000 - Every month 1001 - Every year(1) Note 1: 19.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 202 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 20.0 Note: The programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications.
PIC24FV32KA304 FAMILY 20.1 User Interface 20.1.1 POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN<4:0> bits (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation.
PIC24FV32KA304 FAMILY 20.1.3 DATA SHIFT DIRECTION The LENDIAN bit (CRCCON1<3>) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction of the data that is shifted into the engine.
PIC24FV32KA304 FAMILY REGISTER 20-1: CRCCON1: CRC CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HCS R-1, HCS R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl
PIC24FV32KA304 FAMILY REGISTER 20-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH
PIC24FV32KA304 FAMILY REGISTER 20-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X31 X30 X29 X28 X27 X26 X25 X24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X23 X22 X21 X20 X19 X18 X17 X16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown X<31:16>: XOR of Polynomial Term Xn
PIC24FV32KA304 FAMILY 21.0 An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. HIGH/LOW-VOLTAGE DETECT (HLVD) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV32KA304 FAMILY REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power En
PIC24FV32KA304 FAMILY 22.0 Note: 12-BIT A/D CONVERTER WITH THRESHOLD DETECT This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 12-Bit A/D Converter with Threshold Detect, refer to the “PIC24F Family Reference Manual”, Section 51. “12-Bit A/D Converter with Threshold Detect” (DS39739).
PIC24FV32KA304 FAMILY FIGURE 22-1: 12-BIT A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VREF- VR Select AVDD VR+ 16 VR- VBG Comparator VINH VINL AN0 VRS/H VR+ DAC AN1 12-Bit SAR AN2 Conversion Logic AN3 Data Formatting AN4 VINH AN6 AN7 MUX A AN5 ADC1BUF0: ADC1BUF17 AN8 AD1CON1 AD1CON2 VINL AN9 AD1CON3 AD1CON5 AD1CHS AD1CHITL AN15 CTMU Temp. Sensor CTMU MUX B AN14 AD1CHITH AD1CSSL AD1CSSH VINH VINL Sample Control VBG 0.785 * VDD 0.
PIC24FV32KA304 FAMILY a) b) To perform an A/D conversion: 1. 2. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (ANS<12:10>, ANS<5:0>). b) Select voltage reference source to match expected range on analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and AD1CON3<12:8>).
PIC24FV32KA304 FAMILY 22.1 A/D Control Registers The 12-bit A/D Converter module uses up to 43 registers for its operation. All registers are mapped in the data memory space. 22.1.
PIC24FV32KA304 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 r-0 R/W-0 R/W-0 ADON — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 HSC R/C-0 HSC SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 U = Unimplemented bit, read as ‘0’ Legend: C = Clearable bit r = Reserved bit R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FV32KA304 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS(1) SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM(1) ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG<1:0>: Converte
PIC24FV32KA304 FAMILY REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = RC cloc
PIC24FV32KA304 FAMILY REGISTER 22-4: AD1CON5: A/D CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ASEN LPEN CTMREQ BGREQ VRSREQ — ASINT1 ASINT0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ASEN: Auto-Scan Enable bit 1 = Auto-scan is enabled 0 = A
PIC24FV32KA304 FAMILY REGISTER 22-5: AD1CHS: A/D SAMPLE SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13
PIC24FV32KA304 FAMILY REGISTER 22-6: AD1CHITH: A/D SCAN COMPARE HIT REGISTER (HIGH WORD)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CHH17 CHH16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’.
PIC24FV32KA304 FAMILY REGISTER 22-8: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH WORD)(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — CSS30 CSS29 CSS28 CSS27 CSS26 — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-10 CSS<30:26>: A/D Input Scan Select
PIC24FV32KA304 FAMILY REGISTER 22-10: AD1CTMENH: CTMU ENABLE REGISTER (HIGH WORD)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CTMEN17 CTMEN16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’.
PIC24FV32KA304 FAMILY 22.2 A/D Sampling Requirements The analog input model of the 12-bit A/D Converter is shown in Figure 22-2. The total sampling time for the A/D is a function of the holding capacitor charge time. For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin.
PIC24FV32KA304 FAMILY 22.3 Transfer Function The transfer functions of the A/D Converter in 12-bit resolution are shown in Figure 22-3. The difference of the input voltages, (VINH – VINL), is compared to the reference, ((VR+) – (VR-)). FIGURE 22-3: • The first code transition occurs when the input voltage is ((VR+) – (VR-))/4096 or 1.0 LSb. • The 0000 0000 0001 code is centered at VR- + (1.5 * ((VR+) – (VR-))/4096). • The 0010 0000 0000 code is centered at VREFL + (2048.5 * ((VR+) – (VR-))/4096).
PIC24FV32KA304 FAMILY 23.0 The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the “PIC24F Family Reference Manual”, Section 46.
PIC24FV32KA304 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx VIN- COE - VIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CXINB CXINA VIN- Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 01 COE - CXINC Cx VIN+ CxOUT Pin CXINA VIN- COE - VBG/2 Cx VIN+ CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 CXINB CVREF VIN- CVREF DS39995B-page 226
PIC24FV32KA304 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 CON bit 15 R/W-0 COE R/W-0 CPOL R/W-0 CLPWR U-0 — U-0 — R/W-0 CEVT R-0 COUT bit 8 R/W-0 EVPOL1 bit 7 R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 R/W-0 CCH0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11-10 bit 9 bit 8 bit 7-6 bit 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CON: Comparator
PIC24FV32KA304 FAMILY REGISTER 23-1: bit 4 bit 3-2 bit 1-0 CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED) CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin Unimplemented: Read as ‘0’ CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CxIND pin 01 = Inverting input of comparator connects to CxINC pi
PIC24FV32KA304 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides a range of output voltages, with 32 distinct levels. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV32KA304 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference
PIC24FV32KA304 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the “PIC24F Family Reference Manual”, Section 53. “Charge Time Measurement Unit (CTMU) with Threshold Detect” (DS39743).
PIC24FV32KA304 FAMILY FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP DS39995B-page 232 RPR 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 25.2 When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected.
PIC24FV32KA304 FAMILY REGISTER 25-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimpl
PIC24FV32KA304 FAMILY REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1EDGE EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2 EDG1 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2EDGE EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
PIC24FV32KA304 FAMILY REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED) bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge 0 = Edge 2 is programmed for a negative edge bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Edge 2 source is Comparator 3 output 1110 = Edge 2 source is Comparator 2 output 1101 = Edge 2 source is Comparator 1 output 1100 = Unimplemented; do not use 1011 = Edge 2 source is IC3 1010 = Edge 2 source is IC2 1001 = Edge 2 source is
PIC24FV32KA304 FAMILY REGISTER 25-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change fr
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 238 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 26.0 SPECIAL FEATURES Note: 26.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Watchdog Timer, High-Level Device Integration and Programming Diagnostics, refer to the individual sections of the “PIC24F Family Reference Manual” provided below: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 36.
PIC24FV32KA304 FAMILY REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — GSS0 GWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 GSS0: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled bit 0 GWRP: General Segment Code Flash Write Protec
PIC24FV32KA304 FAMILY REGISTER 26-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 FCKSM1 FCKSM0 R/P-1 R/P-1 R/P-1 R/P-1 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 R/P-1 POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock
PIC24FV32KA304 FAMILY REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN1 WINDIS FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7,5 FWDTEN<1:0>: Watchdog Timer Enable bit 11 = WDT is enabled in hardware 10 = WDT is controlled with the SWDTEN bit setting
PIC24FV32KA304 FAMILY REGISTER 26-6: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE(2) BORV1(3) BORV0(3) I2C1SEL(1) PWRTEN LVRCFG(1) BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(2) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is di
PIC24FV32KA304 FAMILY REGISTER 26-7: R/P-1 DEBUG bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-2 bit 1-0 FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — FICD1 FICD0 bit 0 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled Unimplemented: Read as ‘0’ FICD<
PIC24FV32KA304 FAMILY REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 U-0 DSWDTEN DSBOREN — R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled bit 6 DSBOREN: Deep Sleep/Low-Power BO
PIC24FV32KA304 FAMILY REGISTER 26-9: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bi
PIC24FV32KA304 FAMILY REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Mino
PIC24FV32KA304 FAMILY 26.2 On-Chip Voltage Regulator FIGURE 26-1: All of the PIC24FV32KA304 family of devices power their core digital logic at a nominal 3.0V. This may create an issue for designs that are required to operate at a higher typical voltage, as high as 5.0V. To simplify system design, all devices in the ‘‘FV’’ family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is always enabled and provides power to the core from the other VDD pins.
PIC24FV32KA304 FAMILY The WDT, prescaler and postscaler are reset: 26.3.1 • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e.
PIC24FV32KA304 FAMILY 26.4 Deep Sleep Watchdog Timer (DSWDT) In PIC24FV32KA304 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled. It is driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWCKSEL (FDS<4>). The DSWDT can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler.
PIC24FV32KA304 FAMILY 27.
PIC24FV32KA304 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC24FV32KA304 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FV32KA304 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC24FV32KA304 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24FV32KA304 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C,
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 Non
PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 262 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FV32KA304 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FV32KA304 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FV32KA304 FAMILY 29.1 DC Characteristics Voltage (VDD) FIGURE 29-1: PIC24FV32KA304 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 5.5V 5.5V 3.20V 3.20V 2.00V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz *(VDD – 2.0) + 8 MHz. Voltage (VDD) FIGURE 29-2: PIC24F32KA304 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 1.8) + 8 MHz.
PIC24FV32KA304 FAMILY TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic
PIC24FV32KA304 FAMILY TABLE 29-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Param Symbol No. DC18 Characteristic HLVD Voltage on VDD HLVDL<3:0> = 0000(2) Transition HLVDL<3:0> = 0001 VHLVD Typ Max Units — — 1.90 V 1.88 — 2.13 V HLVDL<3:0> = 0010 2.09 — 2.35 V HLVDL<3:0> = 0011 2.25 — 2.53 V HLVDL<3:0> = 0100 2.35 — 2.
PIC24FV32KA304 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Typical Max Units Conditions IDD Current DC20 — -40°C DC20a — +25°C 269.00 µA 2.0V DC20b — +60°C DC20c 450.00 +85°C PIC24FV32KA3XX DC20d — -40°C DC20e — +25°C 465.00 µA 5.0V DC20f — +60°C DC20g 830.00 +85°C 0.
PIC24FV32KA304 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Typical Max Units Conditions IDD Current (Continued) DC24 — -40°C DC24a — +25°C PIC24FV32KA3XX 13.00 mA 5.0V DC24b — +60°C DC24c 20.00 +85°C 16 MIPS, FOSC = 32 MHz DC24d — -40°C DC24e — +25°C PIC24F32KA3XX 12.00 mA 3.
PIC24FV32KA304 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Typical Max Units Conditions Idle Current (IIDLE) DC40 — -40°C DC40a — +25°C 120.00 DC40b DC40c DC40d 160.00 DC40f µA 200.00 PIC24FV32KA3XX DC40e — +60°C +85°C — -40°C — +25°C — µA +60°C DC40g 430.
PIC24FV32KA304 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Typical Max Units Conditions Idle Current (IIDLE) (Continued) DC46 — DC46a 0.65 DC46b DC46c DC46d 1.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Parameter No. Typical(1) Device Max Units Conditions Power-Down Current (IPD) DC60 — DC60a 6.00 DC60b DC60c DC60d PIC24FV32KA3XX DC60e 6.00 DC60f 8.00 8.50 -40°C µA +25°C +60°C 9.00 +85°C — -40°C 8.00 9.00 µA +25°C +60°C DC60g 10.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Parameter No. Typical(1) Device Max Units Conditions Power-Down Current (IPD) (Continued) DC70 — -40°C DC70a — +25°C 0.03 DC70b DC70c DC70d 0.10 DC70f µA — PIC24FV32KA3XX DC70e — +60°C +85°C — -40°C — +25°C — µA +60°C DC70g 1.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Parameter No. Typical(1) Device Max Units Conditions Power-Down Current (IPD) (Continued) DC71 — DC71a 0.50 DC71b DC71c DC71d PIC24FV32KA3XX DC71e 0.70 DC71f — — -40°C µA +25°C +60°C — +85°C — -40°C — — µA +25°C +60°C DC71g 1.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Parameter No. Typical(1) Device Max Units Conditions Power-Down Current (IPD) (Continued) DC75 — DC75a 5.40 DC75b DC75c DC75d 8.10 DC75f — µA — PIC24FV32KA3XX DC75e — -40°C +25°C +60°C +85°C — -40°C — +25°C — µA +60°C DC75g 14.
PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Parameter No. Typical(1) Device Max Units Conditions Power-Down Current (IPD) (Continued) DC78 — DC78a 0.03 DC78b DC78c DC78d PIC24FV32KA3XX DC78e 0.05 DC78f — — -40°C µA +25°C +60°C — +85°C — -40°C — — µA +25°C +60°C DC78g 0.
PIC24FV32KA304 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VIL Characteristic Input Low Voltage(4) Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial Min Typ(1) Max Units — — — — Conditions DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.
PIC24FV32KA304 FAMILY TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 Output Low Voltage All I/O Pins DO16 OSC2/CLKO VOH DO20 Min Typ(1) — — Max Units Conditions — — 0.4 V IOL = 8.0 mA VDD = 4.5V — — 0.4 V IOL = 4.0 mA VDD = 3.6V — — 0.4 V IOL = 3.5 mA VDD = 2.0V — — 0.4 V IOL = 2.0 mA VDD = 4.5V — — 0.4 V IOL = 1.2 mA VDD = 3.6V — — 0.4 V IOL = 0.4 mA VDD = 2.0V 3.8 — — V IOH = -3.5 mA VDD = 4.
PIC24FV32KA304 FAMILY TABLE 29-12: DC CHARACTERISTICS: DATA EEPROM MEMORY Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Param No. Sym Min Typ(1) 100,000 VMIN Characteristic Max Units — — E/W — 3.
PIC24FV32KA304 FAMILY TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. Characteristics Min Typ Max Units VBG Band Gap Reference Voltage 0.973 1.024 1.075 V TBG Band Gap Reference Start-up Time — 1 — ms VRGOUT Regulator Output Voltage 3.1 3.3 3.6 V CEFC External Filter Capacitor Value 4.7 10 — F VLVR Low-Voltage Regulator Output Voltage — 2.
PIC24FV32KA304 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FV32KA304 family AC characteristics and timing parameters. TABLE 29-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature-40°C TA +85°C for Industrial Operating voltage VDD range as described in Section 29.1 “DC Characteristics”.
PIC24FV32KA304 FAMILY FIGURE 29-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS31 OS30 OS31 OS25 CLKO OS40 OS41 TABLE 29-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param Sym No.
PIC24FV32KA304 FAMILY TABLE 29-20: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
PIC24FV32KA304 FAMILY FIGURE 29-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 29-3 for load conditions. TABLE 29-24: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No.
PIC24FV32KA304 FAMILY TABLE 29-25: COMPARATOR TIMINGS Param No. Symbol Characteristic Min Typ Max Units 300 TRESP Response Time*(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to Output Valid* — — 10 s * Note 1: Comments Parameters are characterized but not tested. Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-26: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param No.
PIC24FV32KA304 FAMILY TABLE 29-27: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 1.8 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.
PIC24FV32KA304 FAMILY TABLE 29-28: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ Max.
PIC24FV32KA304 FAMILY TABLE 29-29: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: AC CHARACTERISTICS Operating temperature Param Symbol No. Characteristic 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C TA +85°C for Industrial Min. Typ(1) Max.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 288 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 20-Lead PDIP (300 mil) Example PIC24FV32KA301 -I/P e3 1010017 28-Lead SPDIP (.300”) Example PIC24FV32KA302 -I/SP e3 1010017 20-Lead SSOP (5.30 mm) Example PIC24FV32KA 301-I/SS e3 1010017 28-Lead SSOP (5.30 mm) Example PIC24FV32KA 302-I/SS e3 1010017 Legend: XX...
PIC24FV32KA304 FAMILY 20-Lead SOIC (7.50 mm) Example PIC24FV32KA301 -I/SO e3 1010017 28-Lead SOIC (7.50 mm) Example PIC24FV32KA302 -I/SO e3 1010017 28-Lead QFN (6x6 mm) Example PIC24FV32KA 302-I/ML e3 1010017 DS39995B-page 290 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 44-Lead QFN (8x8x0.9 mm) Example PIC24FV32KA 304-I/ML e3 1010017 44-Lead TQFP (10x10x1 mm) Example PIC24FV32KA 304-I/PT e3 1010017 48-Lead UQFN (6x6x0.5 mm) Example PIC24FV32KA 304-I/MV e3 1010017 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 30.2 Package Details The following sections give the technical details of the packages. 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 eB e b 6 &! ' ! 9 ' &! 7"') % ! 7,8.
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PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY , - ) " . / 010 ,- 2 # '&& + . # 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 D ! ! & 4 % & & # & D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC24FV32KA304 FAMILY , - ) " . / 010 ,- 2 # '&& + . # 3 & ' !& " & 4 && 255*** ' '5 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 33 , - ) " . / 1 ,- 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 D ! ! & 4 % & & # & D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 ? 1 , > & # %% , & & 4 !! - : 8 & ; & : 7: = #& . .
PIC24FV32KA304 FAMILY 33 , - ) " . / 1 ,- 3 & ' !& " & 4 && 255*** ' '5 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY 33 4# , - 5 " 4 6 16 16 ) ' 4,- 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % 9 9 # & : 8 & #! 99 . .
PIC24FV32KA304 FAMILY 33 4# , - 5 " 4 6 16 16 ) ' 4,- 3 & ' !& " & 4 && 255*** ' '5 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39995B-page 308 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 310 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY APPENDIX A: REVISION HISTORY Revision A (March 2011) Original data sheet for the PIC24FV32KA304 family of devices. Revision B (April 2011) Section 25.0 “Charge Time Measurement Unit (CTMU)” was revised to change the description of the IRNG bits in CTMUICON (Register 25-3). Setting ‘01’ is the base current level (0.55 A nominal) and setting ‘00’ is 1000x base current. Section 29.
PIC24FV32KA304 FAMILY NOTES: DS39995B-page 312 2011 Microchip Technology Inc.
PIC24FV32KA304 FAMILY INDEX A A/D Control Registers ..................................................... 214 AD1CHITH/L .................................................... 214 AD1CHS .......................................................... 214 AD1CON1 ........................................................ 214 AD1CON2 ........................................................ 214 AD1CON3 ........................................................ 214 AD1CON5 .................................................
PIC24FV32KA304 FAMILY CRC Registers .................................................................. 205 Typical Operation ..................................................... 205 User Interface .......................................................... 204 Data ................................................................. 204 Data Shift Direction .......................................... 205 Interrupt Operation ........................................... 205 Polynomial .............................
PIC24FV32KA304 FAMILY O On-Chip Voltage Regulator .............................................. 248 Oscillator Configuration Clock Switching ........................................................ 123 Sequence ......................................................... 123 Configuration Values for Clock Selection ................. 118 CPU Clocking Scheme ............................................ 118 Initial Configuration on POR .................................... 118 Reference Clock Output .............
PIC24FV32KA304 FAMILY I2CxSTAT (I2Cx Status) .......................................... 178 I2CxxCON (I2Cx Control) ........................................ 176 ICxCON1 (Input Capture x Control 1) ...................... 153 ICxCON2 (Input Capture x Control 2) ...................... 154 IEC0 (Interrupt Enable Control 0) .............................. 93 IEC1 (Interrupt Enable Control 1) .............................. 94 IEC2 (Interrupt Enable Control 2) ..............................
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