Datasheet

PIC24FJ256GA110 FAMILY
DS30009905F-page 38  2007-2019 Microchip Technology Inc.
4.2 Data Address Space
The PIC24F core has a separate, 16-bit wide data mem-
ory space, addressable as a single linear range. The
Data Space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The Data Space memory map is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the Data
Space. This gives a Data Space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA[15] = 0) is used for
implemented memory addresses, while the upper half
(EA[15] = 1) is reserved for the Program Space Visibility
area (see Section 4.3.3 “Reading Data from Program
Memory Using Program Space Visibility”).
PIC24FJ256GA110 family devices implement a total of
16 Kbytes of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data are
aligned in data memory and registers as 16-bit words,
but all Data Space EAs resolve to bytes. The Least Sig-
nificant Bytes (LSBs) of each word have even
addresses, while the Most Significant Bytes (MSBs)
have odd addresses.
FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ256GA110 FAMILY DEVICES
0000h
07FEh
FFFEh
LSB
Address
LSBMSB
MSB
Address
0001h
07FFh
1FFFh
FFFFh
8001h
8000h
7FFFh
0801h
0800h
2001h
Near
1FFEh
SFR
SFR Space
Data RAM
2000h
7FFFh
Program Space
Visibility Area
Note: Data memory areas are not shown to scale.
47FEh
4800h
47FFh
4801h
Space
Data Space
Implemented
Data RAM
Unimplemented
Read as ‘0’