Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 35
PIC24FJ256GA110 FAMILY
4.0 MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the Data Space
during code execution.
4.1 Program Address Space
The program address memory space of the
PIC24FJ256GA110 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or Data Space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG[7] to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ256GA110 family of
devices are shown in Figure 4-1.
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information,
refer to “PIC24F Flash Program Mem-
ory” (www.microchip.com/DS30009715)
and “PIC24F Data Memory”
(www.microchip.com/DS30009717) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.