Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 325
PIC24FJ256GA110 FAMILY
T
Timer1 .............................................................................. 157
Timer2/3 and Timer4/5 ..................................................... 159
Timing Diagrams
CLKO and I/O Characteristics .................................. 286
External Clock Requirements .................................. 284
I
2
C Bus Data (Master Mode) .................................... 298
I
2
C Bus Data (Slave Mode) ...................................... 300
I
2
C Bus Start/Stop Bits (Master Mode) .................... 297
I
2
C Bus Start/Stop Bits (Slave Mode) ...................... 299
Input Capture ........................................................... 291
Output Compare ...................................................... 296
Parallel Master Port Read ........................................ 302
Parallel Master Port Write ........................................ 303
Parallel Slave Port ................................................... 301
PWM Requirements ................................................. 296
Reset, Watchdog Timer. Oscillator Start-up Timer,
Power-up Timer Characteristics .............. 272, 289
SPIx Master Mode (CKE = 0) .................................. 292
SPIx Master Mode (CKE = 1) .................................. 293
SPIx Slave Mode (CKE = 0) .................................... 294
SPIx Slave Mode (CKE = 1) .................................... 295
UART Baud Rate Generator Output ........................ 290
UART Start Bit Edge Detection ................................ 290
Timing Requirements
Input Capture ........................................................... 291
Output Compare ...................................................... 296
Parallel Slave Port ................................................... 301
PWM ........................................................................ 296
SPIx Slave Mode (CKE = 1) .................................... 295
Triple Comparator Module ............................................... 237
U
UART
Baud Rate Generator (BRG) ................................... 196
IrDA Support ............................................................ 197
Operation of UxCTS
and UxRTS Pins ..................... 197
Receiving ................................................................. 197
Transmitting
8-Bit Data Mode ............................................... 197
9-Bit Data Mode ............................................... 197
Break and Sync Sequence .............................. 197
Universal Asynchronous Receiver Transmitter. See UART.
V
VDDCORE/VCAP Pin .......................................................... 254
Voltage Regulator (On-Chip) ........................................... 254
and BOR .................................................................. 255
and POR .................................................................. 255
Power-up Requirements .......................................... 255
Standby Mode ......................................................... 255
Tracking Mode ......................................................... 254
W
Watchdog Timer (WDT) ................................................... 255
Control Register ....................................................... 256
Windowed Operation ............................................... 256
WWW Address ................................................................ 326
WWW, On-Line Support ...................................................... 6