Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 323
PIC24FJ256GA110 FAMILY
J
JTAG Interface ................................................................. 258
M
Microchip Internet Web Site ............................................. 326
N
Near Data Space ............................................................... 39
O
Oscillator Configuration
Bit Values for Clock Selection .................................. 118
Clock Switching ........................................................ 122
Sequence ......................................................... 123
Control Registers ..................................................... 119
CPU Clocking Scheme ............................................ 118
Initial Configuration on POR .................................... 118
Reference Clock Output ........................................... 124
Output Compare
Cascaded (32-Bit) Mode .......................................... 169
Operations ............................................................... 170
Synchronous and Trigger Modes ............................. 169
Output Compare with Dedicated Timer ............................ 169
P
Packaging ........................................................................ 305
Details ...................................................................... 307
Marking .................................................................... 305
Parallel Master Port. See PMP.
Peripheral Enable Bits ..................................................... 128
Peripheral Module Disable Bits ........................................ 128
Peripheral Pin Select (PPS) ............................................. 131
Alternate Fixed Pin Mapping .................................... 132
Available Peripherals and Pins ................................ 132
Configuration Control ............................................... 135
Considerations for Use ............................................ 136
Control Registers ..................................................... 137
Input Mapping .......................................................... 132
Mapping Exceptions ................................................. 135
Output Mapping ....................................................... 132
Peripheral Priority .................................................... 132
Selectable Input Sources ......................................... 133
Selectable Output Sources ...................................... 134
Pinout Descriptions ...................................................... 15–22
PMSLP Bit .......................................................................... 68
and Wake-up Time ........................................... 127, 255
Power-Saving Features ................................................... 127
Modes
Doze ................................................................ 128
Idle ................................................................... 128
Sleep ................................................................ 127
Product Identification System .......................................... 328
Program Memory
Access Using Table Instructions ................................ 56
Address Space ........................................................... 35
Addressing ................................................................. 54
Flash Configuration Words ........................................ 37
Memory Maps ............................................................ 36
Organization ............................................................... 37
Program Space Visibility ............................................ 57
Program Space Visibility (PSV) ......................................... 57
Program Verification ........................................................ 256
Programmer’s Model .......................................................... 29
Pulse-Width Modulation (PWM) Mode ............................. 171
Pulse-Width Modulation. See PWM.
PWM
Duty Cycle and Period ............................................. 172
R
Real-Time Clock and Calendar (RTCC) .......................... 213
Real-Time Clock and Calendar. See RTCC.
Referenced Sources ............................................................ 7
Register Maps
ADC ........................................................................... 50
Comparators .............................................................. 51
CPU Core .................................................................. 40
CRC ........................................................................... 51
CTMU ........................................................................ 50
I
2
C ............................................................................. 46
ICN ............................................................................ 41
Input Capture ............................................................. 44
Interrupt Controller ..................................................... 42
NVM ........................................................................... 53
Output Compare ........................................................ 45
Pad Configuration ...................................................... 49
Parallel Master/Slave Port ......................................... 51
Peripheral Pin Select ................................................. 52
PMD ........................................................................... 53
PORTA ...................................................................... 48
PORTB ...................................................................... 48
PORTC ...................................................................... 48
PORTD ...................................................................... 48
PORTE ...................................................................... 49
PORTF ...................................................................... 49
PORTG ...................................................................... 49
Real-Time Clock and Calendar ................................. 51
SPI ............................................................................. 47
System ....................................................................... 53
Timers ........................................................................ 43
UART ......................................................................... 47
Registers
AD1CHS (A/D Input Select) ..................................... 232
AD1CON1 (A/D Control 1) ....................................... 229
AD1CON2 (A/D Control 2) ....................................... 230
AD1CON3 (A/D Control 3) ....................................... 231
AD1CSSL (A/D Input Scan Select Low) .................. 234
AD1PCFGH (A/D Port Configuration High) ............. 233
AD1PCFGL (A/D Port Configuration Low) ............... 233
ALCFGRPT (Alarm Configuration) .......................... 217
ALMINSEC (Alarm Minutes and Seconds Value) .... 221
ALMTHDY (Alarm Month and Day Value) ............... 220
ALTRP (Alternate Peripheral Pin Mapping) ............. 156
ALWDHR (Alarm Weekday and Hours Value) ........ 220
CLKDIV (Clock Divider) ........................................... 121
CMSTAT (Comparator Status) ................................ 240
CMxCON (Comparator x Control) ........................... 239
CORCON (CPU Control) ..................................... 33, 78
CRCCON (CRC Control) ......................................... 225
CRCXOR (CRC XOR Polynomial) .......................... 226
CTMUCON (CTMU Control) .................................... 245
CTMUICON (CTMU Current Control) ...................... 246
CVRCON (Comparator Voltage
Reference Control) .......................................... 242
CW1 (Flash Configuration Word 1) ......................... 248
CW2 (Flash Configuration Word 2) ......................... 250
CW3 (Flash Configuration Word 3) ......................... 251
DEVID (Device ID) ................................................... 252
DEVREV (Device Revision) ..................................... 253
I2CxCON (I2Cx Control) .......................................... 190
I2CxMSK (I2Cx Slave Mode Address Mask) ........... 194
I2CxSTAT (I2Cx Status) .......................................... 192