Datasheet

PIC24FJ256GA110 FAMILY
DS30009905F-page 246  2007-2019 Microchip Technology Inc.
bit 3-2 EDG1SEL[1:0]: Edge 1 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
bit 1 EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0 EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
Note 1: If TGEN = 1, the CTEDGx inputs and CTPLS outputs must be assigned to available RPn pins before use.
See Section 10.4 “Peripheral Pin Select (PPS)” for more information.
REGISTER 24-2: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ITRIM[5:0] IRNG[1:0]
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 ITRIM[5:0]: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
...
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG[1:0]
111111 = Minimum negative change from nominal current
...
100010
100001 = Maximum negative change from nominal current
bit 9-8 IRNG[1:0]: Current Source Range Select bits
11 = 100  Base Current
10 = 10  Base Current
01 = Base current level (0.55 µA nominal)
00 = Current source disabled
bit 7-0 Unimplemented: Read as ‘0’