Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 223
PIC24FJ256GA110 FAMILY
20.0 PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
The programmable CRC generator offers the following
features:
• User-Programmable Polynomial CRC Equation
• Interrupt Output
• Data FIFO
The module implements a software configurable CRC
generator. The terms of the polynomial and its length can
be programmed using the X[15:1] bits (CRCXOR[15:1])
and the PLEN[3:0] bits (CRCCON[3:0]), respectively.
Consider the CRC equation:
x
16
+ x
12
+ x
5
+ 1
To program this polynomial into the CRC generator,
the CRC register bits should be set as shown in
Table 20-1.
TABLE 20-1: EXAMPLE CRC SETUP
Note that for the value of X[15:1], the 12th bit and the
5th bit are set to ‘1’, as required by the equation. The
0 bit required by the equation is always XORed. For a
16-bit polynomial, the 16th bit is also always assumed
to be XORed; therefore, the X[15:1] bits do not have the
0 bit or the 16th bit.
A simplified block diagram of the module is shown in
Figure 20-1. The general topology of the shift engine is
shown in Figure 20-2.
FIGURE 20-1: CRC BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information,
refer to “Programmable Cyclic
Redundancy Check (CRC)”
(www.microchip.com/DS39714) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
Bit Name Bit Value
PLEN[3:0] 1111
X[15:1] 000100000010000
Variable FIFO
(8x16 or 16x8)
CRCDAT
CRC Shift Engine
CRCWDAT
FIFO Empty Event
Set CRCIF
Shift Clock (2 F
CY)