Datasheet

PIC24FJ256GA110 FAMILY
DS30009905F-page 210  2007-2019 Microchip Technology Inc.
FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE
FIGURE 18-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE
TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION
FIGURE 18-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, TWO CHIP SELECTS)
PMA[1:0] Output Register (Buffer) Input Register (Buffer)
00 PMDOUT1[7:0] (0) PMDIN1[7:0] (0)
01 PMDOUT1[15:8] (1) PMDIN1[15:8] (1)
10 PMDOUT2[7:0] (2) PMDIN2[7:0] (2)
11 PMDOUT2[15:8] (3) PMDIN2[15:8] (3)
PMD[7:0]
PMRD
PMWR
Master
Address Bus
Data Bus
Control Lines
PMCS1
PMD[7:0]
PMRD
PMWR
PIC24F Slave
PMCS1
PMD[7:0]
PMRD
PMWR
Master
PMCS1
PMA[1:0]
Address Bus
Data Bus
Control Lines
PMRD
PMWR
PIC24F Slave
PMCS1
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2L (2)
PMDOUT2H (3)
PMDIN1L (0)
PMDIN1H (1)
PMDIN2L (2)
PMDIN2H (3)
PMD[7:0]
Write
Address
Decode
Read
Address
Decode
PMA[1:0]
PMRD
PMWR
PMD[7:0]
PMCS1
PMA[13:0]
PIC24F
Address Bus
Data Bus
Control Lines
PMCS2