Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 187
PIC24FJ256GA110 FAMILY
16.0 INTER-INTEGRATED CIRCUIT
(I
2
C)
The Inter-Integrated Circuit (I
2
C) module is a serial inter-
face useful for communicating with other peripheral or
microcontroller devices. These peripheral devices may be
serial EEPROMs, display drivers, A/D Converters, etc.
The I
2
C module supports these features:
• Independent Master and Slave Logic
• 7-Bit and 10-Bit Device Addresses
• General Call Address, as Defined in the I
2
C Protocol
• Clock Stretching to Provide Delays for the
Processor to Respond to a Slave Data Request
• Both 100 kHz and 400 kHz Bus Specifications
• Configurable Address Masking
• Multi-Master modes to Prevent Loss of Messages
in Arbitration
• Bus Repeater mode, Allowing the Acceptance of
All Messages as a Slave Regardless of the
Address
• Automatic SCL
A block diagram of the module is shown in Figure 16-1.
16.1 Peripheral Remapping Options
The I
2
C modules are tied to fixed pin assignments and
cannot be reassigned to alternate pins using Peripheral
Pin Select. To allow some flexibility with peripheral
multiplexing, the I2C2 module in 100-pin devices can
be reassigned to the alternate pins designated as
ASCL2 and ASDA2 during device configuration.
Pin assignment is controlled by the I2C2SEL Configu-
ration bit; programming this bit (= 0) multiplexes the
module to the ASCL2 and ASDA2 pins.
16.2 Communicating as a Master in a
Single Master Environment
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1. Assert a Start condition on SDAx and SCLx.
2. Send the I
2
C device address byte to the slave
with a write indication.
3. Wait for and verify an Acknowledge from the
slave.
4. Send the first data byte (sometimes known as
the command) to the slave.
5. Wait for and verify an Acknowledge from the
slave.
6. Send the serial memory address low byte to the
slave.
7. Repeat Steps 4 and 5 until all data bytes are
sent.
8. Assert a Repeated Start condition on SDAx and
SCLx.
9. Send the device address byte to the slave with
a read indication.
10. Wait for and verify an Acknowledge from the
slave.
11. Enable master reception to receive serial
memory data.
12. Generate an ACK or NACK condition at the end
of a received byte of data.
13. Generate a Stop condition on SDAx and SCLx.
16.3 Clock Stretching
When clock stretching is enabled (STREN = 1) in Slave
mode, it will not occur during the address detect phase.
As a result, the SCLREL bit will not be cleared upon
address reception when the R/W bit is ‘0’. User soft-
ware should read the Acknowledged address from the
receive buffer before the data byte is received. This can
be achieved by configuring the slave interrupt priority
so that the interrupt latency is less time than to receive
the next byte.
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Inter-Integrated Circuit (I
2
C)”
(www.microchip.com/DS70000195) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.