Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 179
PIC24FJ256GA110 FAMILY
To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register.
2. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with the MSTEN bit
(SPIxCON1[5]) = 1.
3. Clear the SPIROV bit (SPIxSTAT[6]).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2[0]).
5. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT[15]).
6. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data are written to the SPIxBUF
register.
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with the MSTEN bit
(SPIxCON1[5]) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx
pin.
6. Clear the SPIROV bit (SPIxSTAT[6]).
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2[0]).
8. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT[15]).
FIGURE 15-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Internal Data Bus
SDIx
SDOx
SSx
/FSYNCx
SCKx
SPIxSR
bit0
Shift Control
Edge
Select
F
CY
Enable
Sync
SPIxBUF
Control
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1[1:0]
SPIxCON1[4:2]
Master Clock
8-Level FIFO
Transmit Buffer
8-Level FIFO
Receive Buffer
Clock
Control
Primary
1:1/4/16/64
Prescaler
Secondary
Prescaler
1:1 to 1:8