Datasheet

PIC18F97J60 FAMILY
DS39762F-page 94  2011 Microchip Technology Inc.
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0
(5)
0000 0000 72, 161
PORTE RE7
(6)
RE6
(6)
RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 72, 159
PORTD RD7
(5)
RD6
(5)
RD5
(5)
RD4
(5)
RD3
(5)
RD2 RD1 RD0 xxxx xxxx 72, 156
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 72, 153
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 72, 150
PORTA RJPU
(6)
— RA5 RA4 RA3 RA2 RA1 RA0 0-0x 0000 72, 147
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 72, 320
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00 72, 318
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 72, 320
BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00 72, 318
ERDPTH
— — — Buffer Read Pointer High Byte ---0 0101 72, 223
ERDPTL Buffer Read Pointer Low Byte 1111 1010 72, 223
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 72, 211
TMR4 Timer4 Register 0000 0000 72, 187
PR4 Timer4 Period Register 1111 1111 72, 187
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 72, 187
CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 72, 193
CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 72, 193
CCP4CON
— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 73, 189
CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 73, 193
CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 73, 193
CCP5CON
— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 73, 189
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 73, 320
RCREG2 EUSART2 Receive Register 0000 0000 73, 327
TXREG2 EUSART2 Transmit Register 0000 0000 73, 329
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 73, 316
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 73, 317
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 73, 212
ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 73, 211
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 73, 212
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 73, 211
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 73, 279
SSP2ADD MSSP2 Address Register (I
2
C™ Slave mode), MSSP2 Baud Rate Reload Register (I
2
C Master mode) 0000 0000 73, 279
SSP2STAT SMP CKE D/A
PSR/WUA BF 0000 0000 73, 270
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73, 271,
281
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 73, 282
GCEN
ACKSTAT ADMSK5
(4)
ADMSK4
(4)
ADMSK3
(4)
ADMSK2
(4)
ADMSK1
(4)
SEN
EDATA Ethernet Transmit/Receive Buffer Register (EDATA<7:0>) xxxx xxxx 73, 223
EIR
— PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF -000 0-00 73, 241
ECON2 AUTOINC PKTDEC ETHEN
— — — — — 100- ---- 73, 228
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Values on
POR, BOR
Details on
Page:
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.