Datasheet
2011 Microchip Technology Inc. DS39762F-page 93
PIC18F97J60 FAMILY
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 71, 183
PSPCON
(5)
IBF OBF IBOV PSPMODE — — — — 0000 ---- 71, 169
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 71, 320
RCREG1 EUSART1 Receive Register 0000 0000 71, 327
TXREG1 EUSART1 Transmit Register xxxx xxxx 71, 329
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 320
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 71, 320
EECON2 Program Memory Control Register (not a physical register) ---- ---- 71, 106
EECON1
— — — FREE WRERR WREN WR — ---0 x00- 71, 107
IPR3 SSP2IP
(5)
BCL2IP
(5)
RC2IP
(6)
TX2IP
(6)
TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 71, 142
PIR3 SSP2IF
(5)
BCL2IF
(5)
RC2IF
(6)
TX2IF
(6)
TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 71, 136
PIE3 SSP2IE
(5)
BCL2IE
(5)
RC2IE
(6)
TX2IE
(6)
TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 71, 139
IPR2 OSCFIP CMIP ETHIP
rBCL1IP— TMR3IP CCP2IP 1111 1-11 71, 141
PIR2 OSCFIF CMIF ETHIF
rBCL1IF— TMR3IF CCP2IF 0000 0-00 71, 135
PIE2 OSCFIE CMIE ETHIE
rBCL1IE— TMR3IE CCP2IE 0000 0-00 71, 138
IPR1 PSPIP
(9)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 71, 140
PIR1 PSPIF
(9)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 71, 134
PIE1 PSPIE
(9)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 71, 137
MEMCON
(5,7)
EBDIS —WAIT1WAIT0— —WM1WM00-00 --00 71, 116
OSCTUNE PPST1 PLLEN
(8)
PPST0 PPRE — — — — 0000 ---- 71, 51
TRISJ
(6)
TRISJ7
(5)
TRISJ6
(5)
TRISJ5
(6)
TRISJ4
(6)
TRISJ3
(5)
TRISJ2
(5)
TRISJ1
(5)
TRISJ0
(5)
1111 1111 71, 167
TRISH
(6)
TRISH7
(6)
TRISH6
(6)
TRISH5
(6)
TRISH4
(6)
TRISH3
(6)
TRISH2
(6)
TRISH1
(6)
TRISH0
(6)
1111 1111 71, 165
TRISG TRISG7
(5)
TRISG6
(5)
TRISG5
(5)
TRISG4 TRISG3
(6)
TRISG2
(6)
TRISG1
(6)
TRISG0
(6)
1111 1111 71, 163
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
(5)
1111 1111 71, 161
TRISE TRISE7
(6)
TRISE6
(6)
TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 71, 159
TRISD TRISD7
(5)
TRISD6
(5)
TRISD5
(5)
TRISD4
(5)
TRISD3
(5)
TRISD2 TRISD1 TRISD0 1111 1111 71, 156
TRISC TRISC7 TRISC6 TRISC5 TRISC4TRISC3TRISC2TRISC1TRISC01111 1111 71, 153
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 71, 150
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 71, 147
LATJ
(6)
LATJ7
(5)
LATJ6
(5)
LATJ5
(6)
LATJ4
(6)
LATJ3
(5)
LATJ2
(5)
LATJ1
(5)
LATJ0
(5)
xxxx xxxx 71, 167
LATH
(6)
LATH7
(6)
LATH6
(6)
LATH5
(6)
LATH4
(6)
LATH3
(6)
LATH2
(6)
LATH1
(6)
LATH0
(6)
xxxx xxxx 71, 165
LATG LATG7
(5)
LATG6
(5)
LATG5
(5)
LATG4 LATG3
(6)
LATG2
(6)
LATG1
(6)
LATG0
(6)
xxxx xxxx 72, 163
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0
(5)
xxxx xxxx 72, 161
LATE LATE7
(6)
LATE6
(6)
LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 72, 159
LATD LATD7
(5)
LATD6
(5)
LATD5
(5)
LATD4
(5)
LATD3
(5)
LATD2 LATD1 LATD0 xxxx xxxx 72, 156
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 72, 153
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 72, 150
LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 00xx xxxx 72, 147
PORTJ
(6)
RJ7
(5)
RJ6
(5)
RJ5
(6)
RJ4
(6)
RJ3
(5)
RJ2
(5)
RJ1
(5)
RJ0
(5)
xxxx xxxx 72, 167
PORTH
(6)
RH7
(6)
RH6
(6)
RH5
(6)
RH4
(6)
RH3
(6)
RH2
(6)
RH1
(6)
RH0
(6)
0000 xxxx 72, 165
PORTG RG7
(5)
RG6
(5)
RG5
(5)
RG4 RG3
(6)
RG2
(6)
RG1
(6)
RG0
(6)
111x xxxx 72, 163
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Values on
POR, BOR
Details on
Page:
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.