Datasheet

 2011 Microchip Technology Inc. DS39762F-page 75
PIC18F97J60 FAMILY
MAIPGH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
MAIPGL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
MABBIPG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu
MACON4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 --00 -000 --00 -uuu --uu
MACON3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MACON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu
EPAUSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0001 0000 0001 0000 000u uuuu
EPAUSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
EFLOCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -000 ---- -000 ---- -uuu
MISTAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- 0000 ---- 0000 ---- uuuu
MAADR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
MAADR5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Reset,
WDT Reset,
RESET Instruction,
Stack Resets,
CM
Reset
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.