Datasheet

 2011 Microchip Technology Inc. DS39762F-page 63
PIC18F97J60 FAMILY
5.0 RESET
The PIC18F97J60 family of devices differentiates
between various kinds of Reset:
a) MCLR Reset during normal operation
b) MCLR
Reset during power-managed modes
c) Power-on Reset (POR)
d) Brown-out Reset (BOR)
e) Configuration Mismatch (CM)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
i) Watchdog Timer (WDT) Reset during execution
This section discusses Resets generated by hard
events (MCLR), power events (POR and BOR) and
Configuration Mismatches (CM). It also covers the
operation of the various start-up timers. Stack Reset
events are covered in Section 6.1.6.4 “Stack Full and
Underflow Resets”. WDT Resets are covered in
Section 25.2 “Watchdog Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower six bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State
of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 10.0 “Interrupts”.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
WDT
Time-out
V
DD Rise
Detect
PWRT
INTRC
POR Pulse
Chip_Reset
Brown-out
Reset
(1)
RESET Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
32 s
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
PWRT
11-Bit Ripple Counter
66 ms
S
R
Q
Configuration Word Mismatch