Datasheet

PIC18F97J60 FAMILY
DS39762F-page 6  2011 Microchip Technology Inc.
Pin Diagrams (Continued)
PIC18F86J65
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
RE2/P2B RE3/P3C
(2)
RE4/P3B
(2)
RE5/P1C
(2)
RE6/P1B
(2)
RE7/ECCP2
(1)
/P2A
(1)
RD0 V
DD
VSS RD1 RD2
RE1/P2C
RE0/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR
RG4/CCP5/P1D
VSS
VDDCORE/VCAP
RF7/SS1
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
V
SS
OSC2/CLKO
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
ENVREG
RF1/AN6/C2OUT
AV
DD
AVSS
RA3/AN3/VREF+
RA2/AN2/V
REF-
RA1/LEDB/AN1 RA0/LEDA/AN0
V
SS
VDD
RA4/T0CKI
RA5/AN4
RC1/T1OSI/ECCP2
(1)
/P2A
(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO1
RH1 RH0
1
2
RH2
RH3
17
18
RH7/AN15/P1B
(2)
RH6/AN14/P1C
(2)
RH5/AN13/P3B
(2)
RH4/AN12/P3C
(2)
RJ5 RJ4
37
50
49
19
20
33 34
35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 7378 77 76 757980
80-Pin TQFP
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.
2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.
RF5/AN10/CV
REF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF6/AN11
VSSPLL VDDPLL RBIAS V
SSTX
TPOUT+ TPOUT- V
DDTX
VDDRX
TPIN+
TPIN-
V
SSRX
PIC18F87J60
PIC18F86J60