Datasheet

 2011 Microchip Technology Inc. DS39762F-page 463
PIC18F97J60 FAMILY
TABLE 28-27: A/D CONVERSION REQUIREMENTS
28.5 Ethernet Specifications and Requirements
TABLE 28-28: REQUIREMENTS FOR ETHERNET TRANSCEIVER EXTERNAL MAGNETICS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period 0.7 25.0
(1)
sTOSC based, VREF  2.0V
TBD 1 s A/D RC mode
131 T
CNV Conversion Time
(not including acquisition time) (Note 2)
11 12 TAD
132 TACQ Acquisition Time (Note 3) 1.4 — s-40C to +85C
135 T
SWC Switching Time from Convert  Sample — (Note 4)
TBD TDIS Discharge Time 0.2 — s
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.
Parameter Min Norm Max Units Conditions
RX Turns Ratio — 1:1 — —
TX Turns Ratio — 1:1 — — Transformer Center Tap = 3.3V
Insertion Loss — — -1.1 dB
Primary Inductance 350 — — H8mA bias
Transformer Isolation 1.5 — — kVrms Required to meet IEEE 802.3™
requirements
Differential to Common-Mode
Rejection
40 — — dB 0.1 to 10 MHz
Return Loss -16 — — dB