Datasheet

PIC18F97J60 FAMILY
DS39762F-page 462  2011 Microchip Technology Inc.
TABLE 28-26: A/D CONVERTER CHARACTERISTICS: PIC18F97J60 FAMILY (INDUSTRIAL)
FIGURE 28-21: A/D CONVERSION TIMING
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
A01 N
R Resolution — — 10 bit VREF  2.0V
A03 EIL Integral Linearity Error — — <±1 LSb VREF  2.0V
A04 E
DL Differential Linearity Error — — <±1 LSb VREF  2.0V
A06 EOFF Offset Error — — <±3 LSb VREF  2.0V
A07 EGN Gain Error — — <±3 LSb VREF  2.0V
A10 — Monotonicity Guaranteed
(1)
—VSS VAIN VREF
A20 VREF Reference Voltage Range
(V
REFH – VREFL)
1.8
3
—
—
—
—
V
V
V
DD  3.0V
V
DD  3.0V
V
REFSUM Reference Voltage Sum
(V
REFH + VREFL)
——AV
DD + 0.5 V
A21 V
REFH Reference Voltage High VREFL —AVDD V
A22 V
REFL Reference Voltage Low AVSS —VREFH V
A25 V
AIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recommended Impedance of
Analog Voltage Source
——2.5k
A50 I
REF VREF Input Current
(2)
—
—
—
—
5
1000
A
A
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: V
REFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
V
REFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY