Datasheet

 2011 Microchip Technology Inc. DS39762F-page 461

PIC18F97J60 FAMILY

FIGURE 28-19: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 28-24: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 28-20: EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 28-25: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS

Param

No.

Symbol Characteristic Min Max Units Conditions

120 T

CKH2DTV SYNC XMIT (MASTER and SLAVE)

Clock High to Data Out Valid — 40 ns

121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns

122 TDTRF Data Out Rise Time and Fall Time — 20 ns

Param.

No.

Symbol Characteristic Min Max Units Conditions

125 T

DTV2CKL SYNC RCV (MASTER and SLAVE)

Data Hold before CKx  (DTx hold time) 10 — ns

126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns

121

120

122

TXx/CKx

RXx/DTx

Note: Refer to Figure 28-3 for load conditions.

125

126

TXx/CKx

RXx/DTx

Note: Refer to Figure 28-3 for load conditions.