Datasheet

PIC18F97J60 FAMILY
DS39762F-page 450  2011 Microchip Technology Inc.
FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 T
MCLMCLR Pulse Width (low) 2 — — s
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
2.8 4.1 5.4 ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 46.2 66 85.8 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
——3TCY + 2 s System clock available
——415s System clock unavailable
(Sleep mode or
primary oscillator off)
38 T
CSD CPU Start-up Time — 200 — s
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 28-3 for load conditions.