Datasheet

 2011 Microchip Technology Inc. DS39762F-page 445
PIC18F97J60 FAMILY
28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 28-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
DC 41.6667 MHz EC Oscillator mode
Oscillator Frequency
(1)
6 25 MHz HS Oscillator mode
1TOSC External CLKI Period
(1)
24 — ns EC Oscillator mode
Oscillator Period
(1)
40 167 ns HS Oscillator mode
2T
CY Instruction Cycle Time
(1)
96 — ns TCY = 4/FOSC, Industrial
3TOSL,
T
OSH
External Clock in (OSC1)
High or Low Time
10 — ns EC Oscillator mode
4T
OSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 7.5 ns EC Oscillator mode
5 Clock Frequency Tolerance — ±50 ppm Ethernet module enabled
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4