Datasheet
2011 Microchip Technology Inc. DS39762F-page 437
PIC18F97J60 FAMILY
Supply Current (IDD)
(2)
All devices 22.0 45.0 A -10°C
V
DD = 2.0V,
V
DDCORE = 2.0V
(4)
FOSC = 32 kHz
(3)
(SEC_RUN mode,
Timer1 as clock)
22.0 45.0 A+25°C
78.0 114.0 A+70°C
All devices 27.0 52.0 A -10°C
V
DD = 2.5V,
V
DDCORE = 2.5V
(4)
27.0 52.0 A+25°C
92.0 135.0 A+70°C
All devices 106.0 168.0 A -10°C
V
DD = 3.3V
(5)
106.0 168.0 A+25°C
188.0 246.0 A+70°C
All devices 18.0 37.0 A -10°C
V
DD = 2.0V,
V
DDCORE = 2.0V
(4)
FOSC = 32 kHz
(3)
(SEC_IDLE mode,
Timer1 as clock)
18.0 37.0 A+25°C
75.0 105.0 A+70°C
All devices 21.0 40.0 A -10°C
V
DD = 2.5V,
V
DDCORE = 2.5V
(4)
21.0 40.0 A+25°C
84.0 98.0 A+70°C
All devices 94.0 152.0 A -10°C
V
DD = 3.3V
(5)
94.0 152.0 A+25°C
182.0 225.0 A+70°C
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F97J60 Family (Industrial) (Continued)
PIC18F97J60 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
A +85°C for industrial
Param
No.
Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to V
DD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all I
DD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V
DD;
MCLR
= VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to V
SS).
5: Voltage regulator enabled (ENVREG = 1, tied to V
DD).
6: For I
ETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for
all testing.